Lines Matching defs:core
28 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
30 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
33 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
35 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
38 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
40 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
43 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
46 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
47 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
48 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
49 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
50 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
58 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
60 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
64 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
65 /* Activate the core output clamps, but not for core 0. */
66 if (core != 0) {
68 BIT(core));
71 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
73 sunxi_cpu_disable_power(cluster, core);
75 /* power down(?) debug core */
76 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
77 /* ??? Activate the core output clamps, but not for core 0 */
78 if (core != 0) {
79 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
82 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
84 sunxi_cpu_disable_power(cluster, core);
91 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
93 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
96 /* Assert CPU core reset */
97 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
99 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
102 BIT(SUNXI_AA64nAA32_OFFSET + core));
104 sunxi_cpu_enable_power(cluster, core);
105 /* Release the core output clamps */
106 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
108 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
109 /* Deassert CPU core reset */
110 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
112 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
114 /* Assert CPU core reset */
115 mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
117 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
120 mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0));
123 sunxi_cpu_enable_power(cluster, core);
125 /* ??? Release the core output clamps ??? */
126 mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
128 mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
129 /* Deassert CPU core reset */
130 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
131 /* power up(?) debug core */
132 mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
140 unsigned int core;
143 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) {
145 (core << MPIDR_AFF0_SHIFT) |