Lines Matching defs:level
30 * power states requested by a CPU for power levels from level 1 to
32 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a
41 * states at each power level in a cache-line aligned per-domain memory,
73 * Check that the maximum power level supported by the platform makes sense
123 * Check that the maximum retention level supported by the platform is less
124 * than the maximum off level.
131 * is valid. If so, it returns the requested states for each power level.
250 * Routine to return the maximum power level to traverse to after a cpu has
260 * level. If it is invalid then it could only have been turned off
261 * earlier. PLAT_MAX_PWR_LVL will be the highest power level a
273 * does not store the requested state for the CPU power level. Hence an
274 * assertion is added to prevent us from accessing the CPU power level.
310 * assertion is added to prevent us from accessing the CPU power level.
452 * states has been done for each power level.
527 * the target power level (end_pwrlvl). It updates the array of requested power
530 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
532 * that level is an ancestor. It passes this information to the platform to
533 * coordinate and return the target power state. If the target state for a level
534 * is RUN then subsequent levels are not considered. At the CPU level, state
538 * The 'state_info' is updated with the target state for each level between the
555 /* For level 0, the requested state will be equivalent
563 /* Get the requested power states for this power level */
569 * this power level and return the target local power state.
587 * the target power state is RUN at a power level < end_pwlvl.
605 * the target power level (end_pwrlvl), and ensures the requested power states
609 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
611 * that level is an ancestor. It passes this information to the platform to
640 /* Get the requested power states for this power level */
646 * this power level and return the target local power state.
669 * specified power level.
689 * state is requested then no power level is turned off and the highest power
690 * level is placed in a standby/retention state.
692 * It also ensures that the state level X will enter is not shallower than the
693 * state level X + 1 will enter.
706 /* Find the target suspend power level */
719 * While traversing from the highest power level to the lowest,
730 /* Find the highest off power level */
739 * If this is not a request for a power down state then max off level
740 * has to be invalid and max retention level has to be a valid power
741 * level.
752 * This function finds the highest power level which will be powered down
768 * This functions finds the level of the highest power domain which will be
784 * This function is passed the highest level in the topology tree that the
786 * from the node index list in order of increasing power domain level in the
793 unsigned int level;
795 /* No locking required for level 0. Hence start locking from level 1 */
796 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) {
797 parent_idx = parent_nodes[level - 1U];
803 * This function is passed the highest level in the topology tree that the
805 * locks in order of decreasing power domain level in the range specified.
811 unsigned int level;
813 /* Unlock top down. No unlocking required for level 0. */
814 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) {
815 parent_idx = parent_nodes[level - 1U];
960 * traverses the node information and finds the highest power level powered
962 * to power on that power level and power levels below it.
965 * coherency at the interconnect level in addition to gic cpu interface.
987 * Get the maximum power domain level to traverse to after this cpu
996 * This function acquires the lock corresponding to each power level so
1049 * This loop releases the lock corresponding to each power level
1121 psci_non_cpu_pd_nodes[idx].level,