Lines Matching defs:state
55 * execution state setting all fields rather than relying on the hw.
69 * If the target execution state is AArch32 then the following
107 * This function performs initializations that are specific to SECURE state
113 el3_state_t *state;
115 state = get_el3state_ctx(ctx);
116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
143 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
170 * This function performs initializations that are specific to REALM state
176 el3_state_t *state;
178 state = get_el3state_ctx(ctx);
179 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
188 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
193 * This function performs initializations that are specific to NON-SECURE state
199 el3_state_t *state;
201 state = get_el3state_ctx(ctx);
202 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
243 * and RAS ERX registers from EL1 and EL2(from any security state)
263 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
314 * initial entrypoint state as specified by the entry_point_info structure.
322 el3_state_t *state;
325 state = get_el3state_ctx(ctx);
369 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
378 * Secure timer registers to EL3, from AArch64 state only, if specified
444 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
445 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
492 * Populate EL3 state so that we've the right context
495 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
496 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
497 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
512 * manages the cpu context used for entry from and exit to the non-secure state.
514 * the secure state. It also uses this library to get access to the non-secure
515 * state cpu context pointers.
518 * will be used to save state upon exception entry from that EL.
531 * and initializations specific to the security state specified in 'ep'
547 /* Perform security state specific initializations */
561 ERROR("Invalid security state\n");
790 * its `cpu_idx` for first use, and sets the initial entrypoint state as
803 * for first use, and sets the initial entrypoint state as specified by the
1396 * state.
1434 * given security state with the given entrypoint
1439 el3_state_t *state;
1444 /* Populate EL3 state so that ERET jumps to the correct entry */
1445 state = get_el3state_ctx(ctx);
1446 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1451 * pertaining to the given security state
1457 el3_state_t *state;
1462 /* Populate EL3 state so that ERET jumps to the correct entry */
1463 state = get_el3state_ctx(ctx);
1464 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1465 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
1470 * pertaining to the given security state using the value and bit position
1478 el3_state_t *state;
1494 state = get_el3state_ctx(ctx);
1495 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
1498 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1503 * given security state.
1508 el3_state_t *state;
1513 /* Populate EL3 state so that ERET jumps to the correct entry */
1514 state = get_el3state_ctx(ctx);
1515 return read_ctx_reg(state, CTX_SCR_EL3);
1521 * the required security state