Lines Matching defs:val
112 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \
115 << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
120 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \
123 << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \
128 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \
131 << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \
136 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \
139 << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \
144 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \
149 (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
153 #define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \
158 (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \
162 #define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
167 (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \
171 #define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \
176 (((val) & \
200 #define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \
205 (((val) & \
210 #define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \
215 (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \
219 #define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \
224 (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \