Lines Matching defs:x0
17 #define CTX_GPREGS_OFFSET U(0x0)
18 #define CTX_GPREG_X0 U(0x0)
58 #define CTX_SCR_EL3 U(0x0)
90 #define CTX_SPSR_EL1 U(0x0)
134 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0))
145 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
175 #define CTX_ACTLR_EL2 U(0x0)
270 #define CTX_FP_Q0 U(0x0)
326 #define CTX_PACIAKEY_LO U(0x0)
344 #define CTX_CPTR_EL3 U(0x0)
380 * AArch64 general purpose register context structure. Usually x0-x18,
512 * parameters in an aapcs_64 call i.e. x0-x7
514 #define set_aapcs_args0(ctx, x0) do { \
515 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
517 #define set_aapcs_args1(ctx, x0, x1) do { \
519 set_aapcs_args0(ctx, x0); \
521 #define set_aapcs_args2(ctx, x0, x1, x2) do { \
523 set_aapcs_args1(ctx, x0, x1); \
525 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
527 set_aapcs_args2(ctx, x0, x1, x2); \
529 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
531 set_aapcs_args3(ctx, x0, x1, x2, x3); \
533 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
535 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
537 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
539 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
541 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
543 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \