Lines Matching defs:base

171 	uintptr_t base = sdmmc2_params.reg_base;
187 	mmio_write_32(base + SDMMC_POWER,
200 	mmio_write_32(base + SDMMC_POWER, sdmmc2_params.dirpol);
205 	mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
209 	mmio_write_32(base + SDMMC_POWER,
233 	uintptr_t base = sdmmc2_params.reg_base;
243 	if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
244 		mmio_write_32(base + SDMMC_CMDR, 0);
323 	mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
331 		mmio_write_32(base + SDMMC_DCTRLR, 0U);
335 		mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
338 	mmio_write_32(base + SDMMC_ARGR, arg_reg);
340 	mmio_write_32(base + SDMMC_CMDR, cmd_reg);
342 	status = mmio_read_32(base + SDMMC_STAR);
354 		status = mmio_read_32(base + SDMMC_STAR);
385 			cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
386 			cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
387 			cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
388 			cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
390 			cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
393 				cmd->resp_data[1] = mmio_read_32(base +
395 				cmd->resp_data[2] = mmio_read_32(base +
397 				cmd->resp_data[3] = mmio_read_32(base +
404 		mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
409 	status = mmio_read_32(base + SDMMC_STAR);
421 		status = mmio_read_32(base + SDMMC_STAR);
433 	mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
434 	mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
479 	uintptr_t base = sdmmc2_params.reg_base;
521 	mmio_write_32(base + SDMMC_CLKCR,
533 	uintptr_t base = sdmmc2_params.reg_base;
545 	sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
552 	mmio_write_32(base + SDMMC_DTIMER, 0);
554 	mmio_write_32(base + SDMMC_DLENR, 0);
556 	mmio_write_32(base + SDMMC_DCTRLR, 0);
571 	mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
573 	mmio_write_32(base + SDMMC_DLENR, size);
576 		mmio_write_32(base + SDMMC_IDMACTRLR,
578 		mmio_write_32(base + SDMMC_IDMABASE0R, buf);
585 	mmio_clrsetbits_32(base + SDMMC_DCTRLR,
599 	uintptr_t base = sdmmc2_params.reg_base;
600 	uintptr_t fifo_reg = base + SDMMC_FIFOR;
622 		status = mmio_read_32(base + SDMMC_STAR);
627 			mmio_write_32(base + SDMMC_DCTRLR,
630 			mmio_write_32(base + SDMMC_ICR,
644 			mmio_write_32(base + SDMMC_ICR,
656 			if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) &&
673 	mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);