Lines Matching defs:hi2c
45 static void notif_i2c_timeout(struct i2c_handle_s *hi2c)
47 hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
48 hi2c->i2c_mode = I2C_MODE_NONE;
49 hi2c->i2c_state = I2C_STATE_READY;
54 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
59 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c,
62 if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
66 hi2c->lock = 1;
68 hi2c->i2c_state = I2C_STATE_BUSY;
71 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
74 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_ANFOFF);
77 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, analog_filter);
80 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
82 hi2c->i2c_state = I2C_STATE_READY;
84 hi2c->lock = 0;
141 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
146 int stm32_i2c_init(struct i2c_handle_s *hi2c,
152 if (hi2c == NULL) {
156 if (hi2c->i2c_state == I2C_STATE_RESET) {
157 hi2c->lock = 0;
160 hi2c->i2c_state = I2C_STATE_BUSY;
162 clk_enable(hi2c->clock);
165 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
168 mmio_write_32(hi2c->i2c_base_addr + I2C_TIMINGR,
172 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR1, I2C_OAR1_OA1EN);
176 mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1,
179 mmio_write_32(hi2c->i2c_base_addr + I2C_OAR1,
184 mmio_write_32(hi2c->i2c_base_addr + I2C_CR2, 0);
188 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_CR2_ADD10);
195 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2,
199 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_OAR2, I2C_DUALADDRESS_ENABLE);
202 mmio_write_32(hi2c->i2c_base_addr + I2C_OAR2,
208 mmio_write_32(hi2c->i2c_base_addr + I2C_CR1,
213 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR1, I2C_CR1_PE);
215 hi2c->i2c_err = I2C_ERROR_NONE;
216 hi2c->i2c_state = I2C_STATE_READY;
217 hi2c->i2c_mode = I2C_MODE_NONE;
219 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter ?
224 clk_disable(hi2c->clock);
228 clk_disable(hi2c->clock);
235 * @param hi2c: I2C handle
238 static void i2c_flush_txdr(struct i2c_handle_s *hi2c)
244 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXIS) !=
246 mmio_write_32(hi2c->i2c_base_addr + I2C_TXDR, 0);
250 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_TXE) ==
252 mmio_setbits_32(hi2c->i2c_base_addr + I2C_ISR,
259 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
266 static int i2c_wait_flag(struct i2c_handle_s *hi2c, uint32_t flag,
270 uint32_t isr = mmio_read_32(hi2c->i2c_base_addr + I2C_ISR);
277 notif_i2c_timeout(hi2c);
278 hi2c->lock = 0;
288 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
293 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
295 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_AF) == 0U) {
303 while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
306 notif_i2c_timeout(hi2c);
307 hi2c->lock = 0;
313 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF);
315 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
317 i2c_flush_txdr(hi2c);
319 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
321 hi2c->i2c_err |= I2C_ERROR_AF;
322 hi2c->i2c_state = I2C_STATE_READY;
323 hi2c->i2c_mode = I2C_MODE_NONE;
325 hi2c->lock = 0;
333 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
338 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
340 while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
342 if (i2c_ack_failed(hi2c, timeout_ref) != 0) {
347 notif_i2c_timeout(hi2c);
348 hi2c->lock = 0;
360 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
365 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
367 while ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
369 if (i2c_ack_failed(hi2c, timeout_ref) != 0) {
374 notif_i2c_timeout(hi2c);
375 hi2c->lock = 0;
387 * @param hi2c: I2C handle
405 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint16_t dev_addr,
419 mmio_clrsetbits_32(hi2c->i2c_base_addr + I2C_CR2, clr_value, set_value);
425 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
433 static int i2c_request_memory_write(struct i2c_handle_s *hi2c,
437 i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_RELOAD_MODE,
440 if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
446 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
450 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
453 if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
458 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
462 if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0, timeout_ref) != 0) {
472 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
480 static int i2c_request_memory_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
484 i2c_transfer_config(hi2c, dev_addr, mem_add_size, I2C_SOFTEND_MODE,
487 if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
493 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
497 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
500 if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
505 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR,
509 if (i2c_wait_flag(hi2c, I2C_FLAG_TC, 0, timeout_ref) != 0) {
518 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
529 static int i2c_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
544 if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
552 clk_enable(hi2c->clock);
554 hi2c->lock = 1;
557 if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, timeout_ref) != 0) {
561 hi2c->i2c_state = I2C_STATE_BUSY_TX;
562 hi2c->i2c_mode = mode;
563 hi2c->i2c_err = I2C_ERROR_NONE;
569 if (i2c_request_memory_write(hi2c, dev_addr, mem_addr,
576 i2c_transfer_config(hi2c, dev_addr, xfer_size,
580 i2c_transfer_config(hi2c, dev_addr, xfer_size,
587 i2c_transfer_config(hi2c, dev_addr, xfer_size,
592 i2c_transfer_config(hi2c, dev_addr, xfer_size,
599 if (i2c_wait_txis(hi2c, timeout_ref) != 0) {
603 mmio_write_8(hi2c->i2c_base_addr + I2C_TXDR, *p_buff);
610 if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0,
617 i2c_transfer_config(hi2c, dev_addr,
623 i2c_transfer_config(hi2c, dev_addr,
637 if (i2c_wait_stop(hi2c, timeout_ref) != 0) {
641 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
643 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
645 hi2c->i2c_state = I2C_STATE_READY;
646 hi2c->i2c_mode = I2C_MODE_NONE;
651 hi2c->lock = 0;
652 clk_disable(hi2c->clock);
660 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
670 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
674 return i2c_write(hi2c, dev_addr, mem_addr, mem_add_size,
680 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
688 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
692 return i2c_write(hi2c, dev_addr, 0, 0,
699 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
710 static int i2c_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
725 if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
733 clk_enable(hi2c->clock);
735 hi2c->lock = 1;
738 if (i2c_wait_flag(hi2c, I2C_FLAG_BUSY, 1, timeout_ref) != 0) {
742 hi2c->i2c_state = I2C_STATE_BUSY_RX;
743 hi2c->i2c_mode = mode;
744 hi2c->i2c_err = I2C_ERROR_NONE;
748 if (i2c_request_memory_read(hi2c, dev_addr, mem_addr,
761 i2c_transfer_config(hi2c, dev_addr, xfer_size,
765 i2c_transfer_config(hi2c, dev_addr, xfer_size,
770 if (i2c_wait_flag(hi2c, I2C_FLAG_RXNE, 0, timeout_ref) != 0) {
774 *p_buff = mmio_read_8(hi2c->i2c_base_addr + I2C_RXDR);
780 if (i2c_wait_flag(hi2c, I2C_FLAG_TCR, 0,
787 i2c_transfer_config(hi2c, dev_addr,
793 i2c_transfer_config(hi2c, dev_addr,
806 if (i2c_wait_stop(hi2c, timeout_ref) != 0) {
810 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
812 mmio_clrbits_32(hi2c->i2c_base_addr + I2C_CR2, I2C_RESET_CR2);
814 hi2c->i2c_state = I2C_STATE_READY;
815 hi2c->i2c_mode = I2C_MODE_NONE;
820 hi2c->lock = 0;
821 clk_disable(hi2c->clock);
829 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
839 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
843 return i2c_read(hi2c, dev_addr, mem_addr, mem_add_size,
849 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
857 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
861 return i2c_read(hi2c, dev_addr, 0, 0,
868 * @param hi2c: Pointer to a struct i2c_handle_s structure that contains
875 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c,
882 if ((hi2c->i2c_state != I2C_STATE_READY) || (hi2c->lock != 0U)) {
886 clk_enable(hi2c->clock);
888 hi2c->lock = 1;
889 hi2c->i2c_mode = I2C_MODE_NONE;
891 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) & I2C_FLAG_BUSY) !=
896 hi2c->i2c_state = I2C_STATE_BUSY;
897 hi2c->i2c_err = I2C_ERROR_NONE;
903 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_OAR1) &
905 mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
910 mmio_write_32(hi2c->i2c_base_addr + I2C_CR2,
923 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
929 notif_i2c_timeout(hi2c);
934 if ((mmio_read_32(hi2c->i2c_base_addr + I2C_ISR) &
936 if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0,
941 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
944 hi2c->i2c_state = I2C_STATE_READY;
950 if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0, timeout_ref) != 0) {
954 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_AF);
956 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR, I2C_FLAG_STOPF);
959 mmio_setbits_32(hi2c->i2c_base_addr + I2C_CR2,
962 if (i2c_wait_flag(hi2c, I2C_FLAG_STOPF, 0,
967 mmio_write_32(hi2c->i2c_base_addr + I2C_ICR,
974 notif_i2c_timeout(hi2c);
977 hi2c->lock = 0;
978 clk_disable(hi2c->clock);