Lines Matching defs:ctl

23 		return (uintptr_t)priv->ctl;
52 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl)
54 	mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
56 		(uintptr_t)&ctl->swctl,  mmio_read_32((uintptr_t)&ctl->swctl));
60 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl)
65 	mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
67 		(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
71 		swstat = mmio_read_32((uintptr_t)&ctl->swstat);
73 			(uintptr_t)&ctl->swstat, swstat);
80 		(uintptr_t)&ctl->swstat, swstat);
83 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl)
86 	mmio_setbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
87 	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,
88 		mmio_read_32((uintptr_t)&ctl->pctrl_0));
92 	mmio_setbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
93 	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,
94 		mmio_read_32((uintptr_t)&ctl->pctrl_1));