Lines Matching defs:priv
276 static void stm32mp1_wait_operating_mode(struct stm32mp_ddr_priv *priv, uint32_t mode)
287 stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
291 (uintptr_t)&priv->ctl->stat, stat);
321 (uintptr_t)&priv->ctl->stat, stat);
325 static void stm32mp1_mode_register_write(struct stm32mp_ddr_priv *priv, uint8_t addr,
338 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
351 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
353 (uintptr_t)&priv->ctl->mrctrl0,
354 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0);
355 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data);
357 (uintptr_t)&priv->ctl->mrctrl1,
358 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1));
368 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
370 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
376 (uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
380 static void stm32mp1_ddr3_dll_off(struct stm32mp_ddr_priv *priv)
382 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1);
383 uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2);
393 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
395 (uintptr_t)&priv->ctl->dbg1,
396 mmio_read_32((uintptr_t)&priv->ctl->dbg1));
407 dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam);
409 (uintptr_t)&priv->ctl->dbgcam, dbgcam);
421 stm32mp1_mode_register_write(priv, 1, mr1);
436 stm32mp1_mode_register_write(priv, 2, mr2);
446 stm32mp1_mode_register_write(priv, 1, mr1);
453 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl,
456 (uintptr_t)&priv->ctl->pwrctl,
457 mmio_read_32((uintptr_t)&priv->ctl->pwrctl));
465 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR);
471 stm32mp_ddr_start_sw_done(priv->ctl);
473 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
475 (uintptr_t)&priv->ctl->mstr,
476 mmio_read_32((uintptr_t)&priv->ctl->mstr));
478 stm32mp_ddr_wait_sw_done_ack(priv->ctl);
490 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
493 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr,
497 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
499 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr,
501 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr,
504 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr,
506 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr,
511 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
513 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
527 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
529 (uintptr_t)&priv->ctl->dbg1,
530 mmio_read_32((uintptr_t)&priv->ctl->dbg1));
562 void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv,
594 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
595 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
596 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
597 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
598 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
599 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
602 if (stm32mp1_ddr_clk_enable(priv, config->info.speed) != 0) {
608 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
609 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
614 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
622 mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc,
625 (uintptr_t)&priv->ctl->dfimisc,
626 mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
628 stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers);
635 mmio_clrbits_32((uintptr_t)&priv->ctl->mstr,
638 (uintptr_t)&priv->ctl->mstr,
639 mmio_read_32((uintptr_t)&priv->ctl->mstr));
642 stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers);
643 stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers);
646 mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0,
650 (uintptr_t)&priv->ctl->init0,
651 mmio_read_32((uintptr_t)&priv->ctl->init0));
653 stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers);
656 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
657 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
658 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
664 stm32mp_ddr_set_reg(priv, REGPHY_REG, &config->p_reg, ddr_registers);
665 stm32mp_ddr_set_reg(priv, REGPHY_TIMING, &config->p_timing, ddr_registers);
672 mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0));
674 (uintptr_t)&priv->phy->mr1,
675 mmio_read_32((uintptr_t)&priv->phy->mr1));
682 stm32mp1_ddrphy_idone_wait(priv->phy);
697 stm32mp1_ddrphy_init(priv->phy, pir);
703 stm32mp_ddr_start_sw_done(priv->ctl);
705 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc,
708 (uintptr_t)&priv->ctl->dfimisc,
709 mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
711 stm32mp_ddr_wait_sw_done_ack(priv->ctl);
719 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
723 stm32mp1_ddr3_dll_off(priv);
734 stm32mp1_refresh_disable(priv->ctl);
752 stm32mp1_ddrphy_init(priv->phy, pir);
755 stm32mp1_ddrphy_idone_wait(priv->phy);
760 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
763 stm32mp_ddr_enable_axi_port(priv->ctl);