Lines Matching defs:phy
54 #define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
56 #define DDRPHY_REG_REG_SIZE 9 /* st,phy-reg */
58 #define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
214 static void stm32mp1_ddrphy_idone_wait(struct stm32mp_ddrphy *phy)
221 pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
224 (uintptr_t)&phy->pgsr, pgsr);
256 (uintptr_t)&phy->pgsr, pgsr);
259 static void stm32mp1_ddrphy_init(struct stm32mp_ddrphy *phy, uint32_t pir)
263 mmio_write_32((uintptr_t)&phy->pir, pir_init);
265 (uintptr_t)&phy->pir, pir_init,
266 mmio_read_32((uintptr_t)&phy->pir));
272 stm32mp1_ddrphy_idone_wait(phy);
382 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1);
383 uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2);
490 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
493 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr,
497 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS);
499 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr,
501 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr,
504 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr,
506 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr,
672 mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0));
674 (uintptr_t)&priv->phy->mr1,
675 mmio_read_32((uintptr_t)&priv->phy->mr1));
682 stm32mp1_ddrphy_idone_wait(priv->phy);
697 stm32mp1_ddrphy_init(priv->phy, pir);
752 stm32mp1_ddrphy_init(priv->phy, pir);
755 stm32mp1_ddrphy_idone_wait(priv->phy);