Lines Matching defs:ctl
44 #define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
45 #define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
46 #define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
48 #define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
50 #define DDRCTL_REG_PERF_SIZE 11 /* st,ctl-perf */
287 stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
291 (uintptr_t)&priv->ctl->stat, stat);
321 (uintptr_t)&priv->ctl->stat, stat);
338 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
351 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
353 (uintptr_t)&priv->ctl->mrctrl0,
354 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0);
355 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data);
357 (uintptr_t)&priv->ctl->mrctrl1,
358 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1));
368 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
370 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &
376 (uintptr_t)&priv->ctl->mrctrl0, mrctrl0);
393 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
395 (uintptr_t)&priv->ctl->dbg1,
396 mmio_read_32((uintptr_t)&priv->ctl->dbg1));
407 dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam);
409 (uintptr_t)&priv->ctl->dbgcam, dbgcam);
453 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl,
456 (uintptr_t)&priv->ctl->pwrctl,
457 mmio_read_32((uintptr_t)&priv->ctl->pwrctl));
471 stm32mp_ddr_start_sw_done(priv->ctl);
473 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);
475 (uintptr_t)&priv->ctl->mstr,
476 mmio_read_32((uintptr_t)&priv->ctl->mstr));
478 stm32mp_ddr_wait_sw_done_ack(priv->ctl);
511 mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl,
527 mmio_clrbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);
529 (uintptr_t)&priv->ctl->dbg1,
530 mmio_read_32((uintptr_t)&priv->ctl->dbg1));
533 static void stm32mp1_refresh_disable(struct stm32mp_ddrctl *ctl)
535 stm32mp_ddr_start_sw_done(ctl);
537 mmio_setbits_32((uintptr_t)&ctl->rfshctl3,
539 mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
540 mmio_clrbits_32((uintptr_t)&ctl->dfimisc,
542 stm32mp_ddr_wait_sw_done_ack(ctl);
545 static void stm32mp1_refresh_restore(struct stm32mp_ddrctl *ctl,
548 stm32mp_ddr_start_sw_done(ctl);
550 mmio_clrbits_32((uintptr_t)&ctl->rfshctl3,
554 mmio_setbits_32((uintptr_t)&ctl->pwrctl,
557 mmio_setbits_32((uintptr_t)&ctl->dfimisc,
559 stm32mp_ddr_wait_sw_done_ack(ctl);
622 mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc,
625 (uintptr_t)&priv->ctl->dfimisc,
626 mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
635 mmio_clrbits_32((uintptr_t)&priv->ctl->mstr,
638 (uintptr_t)&priv->ctl->mstr,
639 mmio_read_32((uintptr_t)&priv->ctl->mstr));
646 mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0,
650 (uintptr_t)&priv->ctl->init0,
651 mmio_read_32((uintptr_t)&priv->ctl->init0));
703 stm32mp_ddr_start_sw_done(priv->ctl);
705 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc,
708 (uintptr_t)&priv->ctl->dfimisc,
709 mmio_read_32((uintptr_t)&priv->ctl->dfimisc));
711 stm32mp_ddr_wait_sw_done_ack(priv->ctl);
734 stm32mp1_refresh_disable(priv->ctl);
760 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
763 stm32mp_ddr_enable_axi_port(priv->ctl);