Lines Matching defs:ctx
209 static int saes_start(struct stm32_saes_context *ctx)
214 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
216 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
219 while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {
229 static void saes_end(struct stm32_saes_context *ctx, int prev_error)
233 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
235 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
239 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
242 static void saes_write_iv(struct stm32_saes_context *ctx)
245 if (does_chaining_mode_need_iv(ctx->cr)) {
250 mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]);
256 static void saes_write_key(struct stm32_saes_context *ctx)
259 if ((ctx->cr & _SAES_CR_KEYSEL_MASK) == (_SAES_CR_KEYSEL_SOFT << _SAES_CR_KEYSEL_SHIFT)) {
263 mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]);
266 if ((ctx->cr & _SAES_CR_KEYSIZE) == _SAES_CR_KEYSIZE) {
268 mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t),
269 ctx->key[i + 4U]);
275 static int saes_prepare_key(struct stm32_saes_context *ctx)
278 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
281 if ((ctx->cr & _SAES_CR_KEYSIZE) != 0U) {
282 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
284 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
287 saes_write_key(ctx);
290 if ((IS_CHAINING_MODE(ECB, ctx->cr) || IS_CHAINING_MODE(CBC, ctx->cr)) &&
291 is_decrypt(ctx->cr)) {
295 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
299 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
302 ret = wait_computation_completed(ctx->base);
307 clear_computation_completed(ctx->base);
310 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
317 static int save_context(struct stm32_saes_context *ctx)
319 if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_CCF) != 0U) {
325 ctx->cr = mmio_read_32(ctx->base + _SAES_CR);
328 if (does_chaining_mode_need_iv(ctx->cr)) {
333 ctx->iv[i] = mmio_read_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t));
338 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
344 static int restore_context(struct stm32_saes_context *ctx)
349 if ((mmio_read_32(ctx->base + _SAES_CR) & _SAES_CR_EN) != 0U) {
355 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
358 mmio_write_32(ctx->base + _SAES_CR, ctx->cr);
361 ret = saes_prepare_key(ctx);
366 saes_write_iv(ctx);
369 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
403 * @param ctx: SAES process context
411 * @note this function doesn't access to hardware but store in ctx the values
415 int stm32_saes_init(struct stm32_saes_context *ctx, bool is_dec,
423 ctx->assoc_len = 0U;
424 ctx->load_len = 0U;
426 ctx->base = saes_pdata.base;
427 ctx->cr = _SAES_CR_RESET_VALUE;
438 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK,
442 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK,
449 SET_CHAINING_MODE(ECB, (uintptr_t)&(ctx->cr));
452 SET_CHAINING_MODE(CBC, (uintptr_t)&(ctx->cr));
455 SET_CHAINING_MODE(CTR, (uintptr_t)&(ctx->cr));
458 SET_CHAINING_MODE(GCM, (uintptr_t)&(ctx->cr));
461 SET_CHAINING_MODE(CCM, (uintptr_t)&(ctx->cr));
475 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_DATATYPE_MASK,
481 mmio_clrbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE);
484 mmio_setbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSIZE);
493 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
500 mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[3 - i]));
508 mmio_write_32((uintptr_t)(ctx->key + i), htobe32(key_u32[7 - i]));
520 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
524 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
528 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
532 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK,
547 mmio_write_32((uintptr_t)(ctx->iv + i), htobe32(iv_u32[3 - i]));
552 return saes_start(ctx);
557 * @param ctx: SAES process context
564 int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
576 ret = restore_context(ctx);
581 ret = wait_computation_completed(ctx->base);
586 clear_computation_completed(ctx->base);
595 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
599 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
606 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 0U]);
607 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 1U]);
608 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 2U]);
609 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 3U]);
611 ret = wait_computation_completed(ctx->base);
616 clear_computation_completed(ctx->base);
620 ctx->assoc_len += AES_BLOCK_SIZE_BIT;
632 saes_end(ctx, ret);
640 * @param ctx: SAES process context
648 int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
663 prev_cr = mmio_read_32(ctx->base + _SAES_CR);
671 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
679 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
687 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
688 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
689 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
690 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
692 ret = wait_computation_completed(ctx->base);
698 data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
699 data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
700 data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
701 data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
703 clear_computation_completed(ctx->base);
707 ctx->load_len += AES_BLOCK_SIZE_BIT;
717 mmio_write_32(ctx->base + _SAES_DINR, block_in[0U]);
718 mmio_write_32(ctx->base + _SAES_DINR, block_in[1U]);
719 mmio_write_32(ctx->base + _SAES_DINR, block_in[2U]);
720 mmio_write_32(ctx->base + _SAES_DINR, block_in[3U]);
722 ret = wait_computation_completed(ctx->base);
729 block_out[0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
730 block_out[1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
731 block_out[2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
732 block_out[3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
734 clear_computation_completed(ctx->base);
738 ctx->load_len += (data_size - i) * UINT8_BIT;
743 saes_end(ctx, ret);
751 * @param ctx: SAES process context
757 int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag,
764 prev_cr = mmio_read_32(ctx->base + _SAES_CR);
766 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
773 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
777 mmio_write_32(ctx->base + _SAES_DINR, 0);
778 mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len);
779 mmio_write_32(ctx->base + _SAES_DINR, 0);
780 mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len);
782 ret = wait_computation_completed(ctx->base);
788 tag_u32[0] = mmio_read_32(ctx->base + _SAES_DOUTR);
789 tag_u32[1] = mmio_read_32(ctx->base + _SAES_DOUTR);
790 tag_u32[2] = mmio_read_32(ctx->base + _SAES_DOUTR);
791 tag_u32[3] = mmio_read_32(ctx->base + _SAES_DOUTR);
793 clear_computation_completed(ctx->base);
798 saes_end(ctx, ret);
805 * @param ctx: SAES process context
813 int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
841 if (last_block && IS_CHAINING_MODE(CBC, ctx->cr) && is_encrypt(ctx->cr) &&
853 ret = restore_context(ctx);
863 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
864 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
865 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
866 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
868 ret = wait_computation_completed(ctx->base);
874 data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
875 data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
876 data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
877 data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
879 clear_computation_completed(ctx->base);
893 ret = save_context(ctx);
899 saes_end(ctx, ret);