Lines Matching defs:base
164 if ((info.base == 0U) || (info.clock < 0) || (info.reset < 0)) {
168 pdata->base = (uintptr_t)info.base;
190 static int wait_computation_completed(uintptr_t base)
194 while ((mmio_read_32(base + _SAES_SR) & _SAES_SR_CCF) != _SAES_SR_CCF) {
204 static void clear_computation_completed(uintptr_t base)
206 mmio_setbits_32(base + _SAES_ICR, _SAES_I_CC);
214 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
216 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
219 while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {
233 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
235 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
239 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
250 mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]);
263 mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]);
268 mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t),
278 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
282 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
284 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_KEYSIZE);
295 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
299 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
302 ret = wait_computation_completed(ctx->base);
307 clear_computation_completed(ctx->base);
310 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK,
319 if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_CCF) != 0U) {
325 ctx->cr = mmio_read_32(ctx->base + _SAES_CR);
333 ctx->iv[i] = mmio_read_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t));
338 mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
349 if ((mmio_read_32(ctx->base + _SAES_CR) & _SAES_CR_EN) != 0U) {
355 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
358 mmio_write_32(ctx->base + _SAES_CR, ctx->cr);
369 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
426 ctx->base = saes_pdata.base;
581 ret = wait_computation_completed(ctx->base);
586 clear_computation_completed(ctx->base);
595 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
599 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
606 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 0U]);
607 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 1U]);
608 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 2U]);
609 mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 3U]);
611 ret = wait_computation_completed(ctx->base);
616 clear_computation_completed(ctx->base);
663 prev_cr = mmio_read_32(ctx->base + _SAES_CR);
671 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
679 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
687 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
688 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
689 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
690 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
692 ret = wait_computation_completed(ctx->base);
698 data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
699 data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
700 data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
701 data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
703 clear_computation_completed(ctx->base);
717 mmio_write_32(ctx->base + _SAES_DINR, block_in[0U]);
718 mmio_write_32(ctx->base + _SAES_DINR, block_in[1U]);
719 mmio_write_32(ctx->base + _SAES_DINR, block_in[2U]);
720 mmio_write_32(ctx->base + _SAES_DINR, block_in[3U]);
722 ret = wait_computation_completed(ctx->base);
729 block_out[0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
730 block_out[1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
731 block_out[2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
732 block_out[3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
734 clear_computation_completed(ctx->base);
764 prev_cr = mmio_read_32(ctx->base + _SAES_CR);
766 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_GCMPH_MASK,
773 mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_EN);
777 mmio_write_32(ctx->base + _SAES_DINR, 0);
778 mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len);
779 mmio_write_32(ctx->base + _SAES_DINR, 0);
780 mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len);
782 ret = wait_computation_completed(ctx->base);
788 tag_u32[0] = mmio_read_32(ctx->base + _SAES_DOUTR);
789 tag_u32[1] = mmio_read_32(ctx->base + _SAES_DOUTR);
790 tag_u32[2] = mmio_read_32(ctx->base + _SAES_DOUTR);
791 tag_u32[3] = mmio_read_32(ctx->base + _SAES_DOUTR);
793 clear_computation_completed(ctx->base);
863 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);
864 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);
865 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);
866 mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);
868 ret = wait_computation_completed(ctx->base);
874 data_out_u32[w + 0U] = mmio_read_32(ctx->base + _SAES_DOUTR);
875 data_out_u32[w + 1U] = mmio_read_32(ctx->base + _SAES_DOUTR);
876 data_out_u32[w + 2U] = mmio_read_32(ctx->base + _SAES_DOUTR);
877 data_out_u32[w + 3U] = mmio_read_32(ctx->base + _SAES_DOUTR);
879 clear_computation_completed(ctx->base);