Lines Matching defs:ret

1785 	int ret;
1791 	ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB,
1793 	if (ret < 0) {
1799 	ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB,
1802 	*csg_set = (ret == 0);
1804 	if (ret == -FDT_ERR_NOTFOUND) {
1805 		ret = 0;
1808 	return ret;
1820 	int ret, len;
1837 	ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
1839 	if (ret < 0) {
1843 	ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB,
1845 	if (ret < 0) {
1860 		ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
1863 		if (ret != 0) {
1864 			return ret;
1906 	ret = stm32mp1_set_clksrc(CLK_MPU_HSI);
1907 	if (ret != 0) {
1908 		return ret;
1910 	ret = stm32mp1_set_clksrc(CLK_AXI_HSI);
1911 	if (ret != 0) {
1912 		return ret;
1914 	ret = stm32mp1_set_clksrc(CLK_MCU_HSI);
1915 	if (ret != 0) {
1916 		return ret;
1951 		ret = stm32mp1_pll_stop(i);
1952 		if (ret != 0) {
1953 			return ret;
1959 		ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]);
1960 		if (ret != 0) {
1961 			return ret;
1971 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
1972 	if (ret != 0) {
1973 		return ret;
1975 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
1976 	if (ret != 0) {
1977 		return ret;
1979 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
1980 	if (ret != 0) {
1981 		return ret;
1983 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1984 	if (ret != 0) {
1985 		return ret;
1987 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
1988 	if (ret != 0) {
1989 		return ret;
1991 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
1992 	if (ret != 0) {
1993 		return ret;
1995 	ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
1996 	if (ret != 0) {
1997 		return ret;
2005 	ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]);
2006 	if (ret != 0) {
2007 		return ret;
2011 		ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]);
2012 		if (ret != 0) {
2013 			return ret;
2018 		ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]);
2019 		if (ret != 0) {
2020 			return ret;
2041 		ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
2042 		if (ret != 0) {
2043 			return ret;
2058 		ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);
2059 		if (ret != 0) {
2060 			return ret;
2069 	ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]);
2070 	if (ret != 0) {
2071 		return ret;
2073 	ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]);
2074 	if (ret != 0) {
2075 		return ret;
2077 	ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]);
2078 	if (ret != 0) {
2079 		return ret;