Lines Matching defs:rcc_base
679 uintptr_t rcc_base = stm32mp_rcc_base();
682 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
687 uintptr_t rcc_base = stm32mp_rcc_base();
690 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask;
744 uintptr_t rcc_base = stm32mp_rcc_base();
771 p_sel = (mmio_read_32(rcc_base + sel->offset) &
798 uintptr_t rcc_base = stm32mp_rcc_base();
800 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1);
801 fracr = mmio_read_32(rcc_base + pll->pllxfracr);
853 uintptr_t rcc_base = stm32mp_rcc_base();
858 reg = mmio_read_32(rcc_base + RCC_MPCKSELR);
872 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR);
886 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR);
902 reg = mmio_read_32(rcc_base + RCC_AXIDIVR);
907 reg = mmio_read_32(rcc_base + RCC_APB4DIVR);
911 reg = mmio_read_32(rcc_base + RCC_APB5DIVR);
923 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR);
942 reg = mmio_read_32(rcc_base + RCC_MCUDIVR);
947 reg = mmio_read_32(rcc_base + RCC_APB1DIVR);
951 reg = mmio_read_32(rcc_base + RCC_APB2DIVR);
955 reg = mmio_read_32(rcc_base + RCC_APB3DIVR);
964 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR);
996 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
1054 uintptr_t rcc_base = stm32mp_rcc_base();
1059 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit));
1061 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit));
1067 uintptr_t rcc_base = stm32mp_rcc_base();
1072 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET,
1075 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit));
1081 uintptr_t rcc_base = stm32mp_rcc_base();
1083 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit);
1233 uintptr_t rcc_base = stm32mp_rcc_base();
1254 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) &
1256 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) &
1265 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) &
1267 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) &
1328 uintptr_t rcc_base = stm32mp_rcc_base();
1331 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP);
1335 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP);
1342 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >>
1352 mmio_clrsetbits_32(rcc_base + RCC_BDCR,
1378 uintptr_t rcc_base = stm32mp_rcc_base();
1381 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP);
1385 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP);
1394 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON);
1398 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) &&
1424 uintptr_t rcc_base = stm32mp_rcc_base();
1425 uintptr_t address = rcc_base + RCC_OCRDYR;
1427 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR,
1473 uintptr_t rcc_base = stm32mp_rcc_base();
1474 uintptr_t pllxcr = rcc_base + pll->pllxcr;
1476 uintptr_t clksrc_address = rcc_base + (clksrc >> 4);
1494 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK;
1514 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) {
1525 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) {
1536 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) {
1606 uintptr_t rcc_base = stm32mp_rcc_base();
1615 mmio_write_32(rcc_base + pll->pllxcfgr2, value);
1622 uintptr_t rcc_base = stm32mp_rcc_base();
1628 src = mmio_read_32(rcc_base + pll->rckxselr) &
1649 mmio_write_32(rcc_base + pll->pllxcfgr1, value);
1653 mmio_write_32(rcc_base + pll->pllxfracr, value);
1656 mmio_write_32(rcc_base + pll->pllxfracr, value);
1659 mmio_write_32(rcc_base + pll->pllxfracr, value);
1813 uintptr_t rcc_base = stm32mp_rcc_base();
1919 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) &
1969 mmio_write_32(rcc_base + RCC_MPCKDIVR,
1971 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR);
1975 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR);
1979 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR);
1983 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR);
1987 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR);
1991 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR);
1995 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR);
2001 mmio_write_32(rcc_base + RCC_RTCDIVR,
2091 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR);
2123 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) &
2142 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR,
2179 uintptr_t rcc_base = stm32mp_rcc_base();
2226 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
2235 p_sel = mmio_read_32(rcc_base + pll->rckxselr) &