Lines Matching defs:pllcfg
1470 uint32_t *pllcfg, int plloff)
1497 (pllcfg[PLLCFG_M] + 1U);
1508 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1510 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1530 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1532 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1534 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1603 uint32_t *pllcfg)
1609 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) &
1611 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) &
1613 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) &
1619 uint32_t *pllcfg, uint32_t fracv)
1632 (pllcfg[PLLCFG_M] + 1U);
1643 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) &
1645 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) &
1661 stm32mp1_pll_config_output(pll_id, pllcfg);
1780 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg,
1792 pllcfg);
1818 unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
1860 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i],
1925 pllcfg[_PLL3],
1933 pllcfg[_PLL4],
2037 stm32mp1_pll_config_output(i, pllcfg[i]);
2041 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]);
2058 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]);