Lines Matching defs:clock
21 #include <dt-bindings/clock/stm32mp1-clksrc.h>
88 /* Lists only the parent clock we are interested in */
116 /* State the parent clock ID straight related to a clock */
578 /* Prescaler table lookups for clock computation */
634 /* RCC clock device driver private */
746 /* Few non gateable clock have a static parent ID, find them */
852 unsigned long clock = 0;
861 clock = stm32mp1_clk_get_fixed(_HSI);
864 clock = stm32mp1_clk_get_fixed(_HSE);
867 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
870 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
874 clock >>= stm32mp1_mpu_div[clkdiv];
889 clock = stm32mp1_clk_get_fixed(_HSI);
892 clock = stm32mp1_clk_get_fixed(_HSE);
895 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
901 /* System clock divider */
903 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
908 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
912 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
926 clock = stm32mp1_clk_get_fixed(_HSI);
929 clock = stm32mp1_clk_get_fixed(_HSE);
932 clock = stm32mp1_clk_get_fixed(_CSI);
935 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
941 /* MCU clock divider */
943 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
948 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
952 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
956 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
967 clock = stm32mp1_clk_get_fixed(_HSI);
970 clock = stm32mp1_clk_get_fixed(_HSE);
973 clock = stm32mp1_clk_get_fixed(_CSI);
981 clock = stm32mp1_clk_get_fixed(_HSI);
985 clock = stm32mp1_clk_get_fixed(_CSI);
989 clock = stm32mp1_clk_get_fixed(_HSE);
992 clock = stm32mp1_clk_get_fixed(_HSE) >> 1;
995 clock = stm32mp1_clk_get_fixed(_HSE);
996 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U;
999 clock = stm32mp1_clk_get_fixed(_LSI);
1002 clock = stm32mp1_clk_get_fixed(_LSE);
1006 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P);
1009 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q);
1012 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R);
1015 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P);
1018 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q);
1021 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R);
1024 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P);
1027 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q);
1030 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R);
1033 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P);
1036 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q);
1039 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R);
1043 clock = USB_PHY_48_MHZ;
1049 return clock;
1056 VERBOSE("Enable clock %u\n", gate->index);
1069 VERBOSE("Disable clock %u\n", gate->index);
1138 /* Enable non-secure clock w/o any refcounting */
2068 /* Configure with expected clock source */
2107 * only if previous clock is still ON
2108 * => deactivated CKPER only after switching clock
2171 * Get the parent ID of the target parent clock, for tagging as secure
2172 * shared clock dependencies.
2285 VERBOSE("Cannot secure parent clock %s\n",
2317 /* Others are expected gateable clock */
2320 INFO("No parent found for clock %lu\n", clock_id);