Lines Matching defs:vco
74 struct stm32_pll_vco vco;
1248 struct stm32_pll_vco *vco,
1251 uint32_t divm = vco->div_mn[PLL_CFG_M];
1252 uint32_t divn = vco->div_mn[PLL_CFG_N];
1289 struct stm32_pll_vco *vco)
1294 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
1306 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);
1312 struct stm32_pll_vco *vco)
1320 if (!vco->csg_enabled) {
1324 mod_per = vco->csg[PLL_CSG_MOD_PER];
1325 inc_step = vco->csg[PLL_CSG_INC_STEP];
1326 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE];
1452 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
1470 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);
1472 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);
1488 if (pll_conf->vco.status != 0U) {
2157 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco)
2161 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn);
2166 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg);
2168 vco->csg_enabled = (err == 0);
2178 vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON;
2180 vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
2182 vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
2227 err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);