Lines Matching defs:subnode

2080 	int subnode = 0;
2085 	fdt_for_each_subnode(subnode, fdt, node) {
2090 		cchar = fdt_get_name(fdt, subnode, &ret);
2096 		    fdt_get_status(subnode) == DT_DISABLED) {
2100 		cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
2107 		if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) {
2111 		if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) {
2115 		if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) {
2119 		osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH);
2157 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco)
2161 	err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn);
2166 	err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg);
2180 	vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);
2182 	vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);
2187 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output)
2191 	err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,
2200 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2207 	cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2247 		int subnode = 0;
2252 		subnode = fdt_subnode_offset(fdt, node, name);
2253 		if (!fdt_check_node(subnode)) {
2257 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);