Lines Matching defs:ret

1076 	int ret;
1080 	ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI);
1081 	if (ret != 0) {
1082 		return ret;
1085 	ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI);
1086 	if (ret != 0) {
1087 		return ret;
1090 	ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI);
1091 	if (ret != 0) {
1092 		return ret;
1110 	int ret;
1117 	ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);
1118 	if (ret != 0) {
1119 		return ret;
1147 		int ret;
1153 		ret = clk_stm32_set_div(priv, div_id, div_n);
1154 		if (ret != 0) {
1155 			return ret;
1167 	int ret;
1188 			ret = stm32_clk_configure_mux(priv, cmd_data);
1200 			ret = stm32_clk_configure_clk(priv, cmd_data);
1203 			ret = -EINVAL;
1207 		if (ret != 0) {
1208 			return ret;
1219 		ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
1220 		if (ret != 0) {
1221 			return ret;
1449 	int ret = 0;
1452 	ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
1453 	if (ret != 0) {
1454 		return ret;
1474 	ret = _clk_stm32_pll_enable(priv, pll);
1475 	if (ret != 0) {
1476 		return ret;
1524 	int ret = 0;
1527 		ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
1530 	return ret;
1994 	int ret;
2011 	ret = stm32mp1_come_back_to_hsi();
2012 	if (ret != 0) {
2013 		return ret;
2016 	ret = stm32_clk_hsidiv_configure(priv);
2017 	if (ret != 0) {
2018 		return ret;
2021 	ret = stm32_clk_stgen_configure(priv, _STGENC);
2022 	if (ret != 0) {
2026 	ret = stm32_clk_dividers_configure(priv);
2027 	if (ret != 0) {
2031 	ret = stm32_clk_pll_configure(priv);
2032 	if (ret != 0) {
2037 	ret = stm32_clk_oscillators_wait_lse_ready(priv);
2038 	if (ret != 0) {
2043 	ret = stm32_clk_source_configure(priv);
2044 	if (ret != 0) {
2049 	ret = stm32_clk_oscillators_lse_set_css(priv);
2050 	if (ret != 0) {
2055 	ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p);
2056 	if (ret != 0) {
2057 		return ret;
2061 	ret = stm32_clk_stgen_configure(priv, _STGENC);
2062 	if (ret != 0) {
2088 		int ret = 0;
2090 		cchar = fdt_get_name(fdt, subnode, &ret);
2092 			return ret;
2095 		if (strncmp(cchar, name, (size_t)ret) ||
2100 		cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
2102 			return ret;
2312 	int ret;
2314 	ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata);
2315 	if (ret != 0) {
2316 		return ret;
2319 	ret = clk_stm32_init(&stm32mp13_clock_data, base);
2320 	if (ret != 0) {
2321 		return ret;
2324 	ret = stm32mp1_init_clock_tree();
2325 	if (ret != 0) {
2326 		return ret;