Lines Matching defs:priv
955 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx,
958 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx);
966 address = priv->base + bypass_data->offset;
974 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)
976 struct stm32_clk_platdata *pdata = priv->pdata;
982 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {
986 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);
988 _clk_stm32_enable(priv, _CK_HSE);
991 clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass);
994 clk_oscillator_set_css(priv, _CK_HSE, css);
997 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)
999 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);
1000 struct stm32_clk_platdata *pdata = priv->pdata;
1006 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {
1010 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
1012 clk_oscillator_set_drive(priv, _CK_LSE, drive);
1014 _clk_stm32_gate_enable(priv, osc_data->gate_id);
1064 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv)
1066 struct stm32_clk_platdata *pdata = priv->pdata;
1069 clk_oscillator_set_css(priv, _CK_LSE, osci->css);
1077 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1080 ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI);
1085 ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI);
1090 ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI);
1098 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)
1102 return clk_get_index(priv, binding_id);
1105 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
1112 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);
1117 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);
1123 clk_stm32_enable_call_ops(priv, clk_id);
1125 clk_stm32_disable_call_ops(priv, clk_id);
1131 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)
1136 return clk_mux_set_parent(priv, mux, sel);
1139 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv)
1141 struct stm32_clk_platdata *pdata = priv->pdata;
1153 ret = clk_stm32_set_div(priv, div_id, div_n);
1162 static int stm32_clk_source_configure(struct stm32_clk_priv *priv)
1164 struct stm32_clk_platdata *pdata = priv->pdata;
1188 ret = stm32_clk_configure_mux(priv, cmd_data);
1192 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data);
1195 if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) {
1200 ret = stm32_clk_configure_clk(priv, cmd_data);
1219 ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED);
1228 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id)
1232 stgen_freq = _clk_stm32_get_rate(priv, id);
1246 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv,
1256 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);
1287 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv,
1291 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1294 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
1310 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,
1314 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1336 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,
1339 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1349 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1350 struct stm32_clk_platdata *pdata = priv->pdata;
1355 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1357 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1362 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1364 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1371 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1373 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1382 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
1385 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1400 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
1403 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1418 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1420 if (_clk_stm32_pll_is_enabled(priv, pll)) {
1425 _clk_stm32_pll_set_on(priv, pll);
1428 return _clk_stm32_pll_wait_ready_on(priv, pll);
1431 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1433 if (!_clk_stm32_pll_is_enabled(priv, pll)) {
1438 _clk_stm32_pll_set_off(priv, pll);
1441 _clk_stm32_pll_wait_ready_off(priv, pll);
1444 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,
1448 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1452 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);
1459 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1468 _clk_stm32_pll_disable(priv, pll);
1470 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);
1471 clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1472 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);
1474 ret = _clk_stm32_pll_enable(priv, pll);
1484 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)
1489 return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
1495 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv)
1499 err = clk_stm32_pll_init(priv, _PLL1);
1504 err = clk_stm32_pll_init(priv, _PLL2);
1509 err = clk_stm32_pll_init(priv, _PLL3);
1514 err = clk_stm32_pll_init(priv, _PLL4);
1522 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)
1526 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {
1527 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
1533 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)
1535 stm32_enable_oscillator_hse(priv);
1536 stm32_enable_oscillator_lse(priv);
1537 _clk_stm32_enable(priv, _CK_LSI);
1538 _clk_stm32_enable(priv, _CK_CSI);
1541 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv)
1543 return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI));
1547 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p)
1559 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p)
1568 _usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
1569 _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
1635 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
1638 const struct clk_stm32 *clk = _clk_get(priv, id);
1641 uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1673 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)
1675 const struct clk_stm32 *clk = _clk_get(priv, id);
1679 return _clk_stm32_pll_is_enabled(priv, pll);
1682 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)
1684 const struct clk_stm32 *clk = _clk_get(priv, id);
1688 return _clk_stm32_pll_enable(priv, pll);
1691 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)
1693 const struct clk_stm32 *clk = _clk_get(priv, id);
1697 _clk_stm32_pll_disable(priv, pll);
1722 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv,
1725 const struct clk_stm32 *clk = _clk_get(priv, idx);
1728 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate);
1731 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx)
1733 const struct clk_stm32 *clk = _clk_get(priv, idx);
1736 return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id);
1739 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx)
1741 const struct clk_stm32 *clk = _clk_get(priv, idx);
1744 return _clk_stm32_gate_enable(priv, composite_cfg->gate_id);
1747 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx)
1749 const struct clk_stm32 *clk = _clk_get(priv, idx);
1752 _clk_stm32_gate_disable(priv, composite_cfg->gate_id);
1993 struct stm32_clk_priv *priv = clk_stm32_get_priv();
1997 int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K);
1998 int usbo_p = _clk_stm32_get_parent(priv, _USBO_K);
2001 pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p);
2008 stm32_clk_oscillators_enable(priv);
2016 ret = stm32_clk_hsidiv_configure(priv);
2021 ret = stm32_clk_stgen_configure(priv, _STGENC);
2026 ret = stm32_clk_dividers_configure(priv);
2031 ret = stm32_clk_pll_configure(priv);
2037 ret = stm32_clk_oscillators_wait_lse_ready(priv);
2043 ret = stm32_clk_source_configure(priv);
2049 ret = stm32_clk_oscillators_lse_set_css(priv);
2055 ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p);
2061 ret = stm32_clk_stgen_configure(priv, _STGENC);
2067 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR,