Lines Matching defs:pll

82 	struct stm32_pll_dt_cfg *pll;
1247 				       const struct stm32_clk_pll *pll,
1256 	prate = _clk_stm32_get_parent_rate(priv, pll->clk_id);
1259 	if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) ||
1260 	    (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) {
1266 	if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) {
1288 				     const struct stm32_clk_pll *pll,
1291 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1294 	if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {
1311 				     const struct stm32_clk_pll *pll,
1314 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1336 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll,
1339 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1352 	return &pdata->pll[pll_idx];
1355 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1357 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1362 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1364 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1371 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1373 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1383 					const struct stm32_clk_pll *pll)
1385 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1392 			      pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
1401 					 const struct stm32_clk_pll *pll)
1403 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1410 			      pll->clk_id, pll->reg_pllxcr, mmio_read_32(pll_base));
1418 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1420 	if (_clk_stm32_pll_is_enabled(priv, pll)) {
1425 	_clk_stm32_pll_set_on(priv, pll);
1428 	return _clk_stm32_pll_wait_ready_on(priv, pll);
1431 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
1433 	if (!_clk_stm32_pll_is_enabled(priv, pll)) {
1438 	_clk_stm32_pll_set_off(priv, pll);
1441 	_clk_stm32_pll_wait_ready_off(priv, pll);
1447 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx);
1448 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1459 		clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1468 	_clk_stm32_pll_disable(priv, pll);
1470 	clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);
1471 	clk_stm32_pll_config_out(priv, pll, &pll_conf->output);
1472 	clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);
1474 	ret = _clk_stm32_pll_enable(priv, pll);
1640 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1641 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;
1677 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1679 	return _clk_stm32_pll_is_enabled(priv, pll);
1686 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1688 	return _clk_stm32_pll_enable(priv, pll);
1695 	const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id);
1697 	_clk_stm32_pll_disable(priv, pll);
1967 	.pll		= mp13_pll,
2200 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
2207 	cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
2227 	err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);
2232 	err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output);
2245 		struct stm32_pll_dt_cfg *pll = &pdata->pll[i];
2250 		snprintf(name, sizeof(name), "st,pll@%u", i);
2257 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);