Lines Matching defs:priv
59 struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id)
61 const struct clk_stm32 *clk = _clk_get(priv, id);
65 return &priv->osci_data[osc_id];
68 void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass)
70 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
79 address = priv->base + bypass_data->offset;
90 void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css)
92 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
101 address = priv->base + css_data->offset;
108 void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv)
110 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
121 address = priv->base + drive_data->offset;
142 int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on)
144 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
146 return _clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, ready_on);
149 int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id)
151 return clk_oscillator_wait_ready(priv, id, true);
154 int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id)
156 return clk_oscillator_wait_ready(priv, id, false);
159 static int clk_gate_enable(struct stm32_clk_priv *priv, int id)
161 const struct clk_stm32 *clk = _clk_get(priv, id);
164 mmio_setbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx));
169 static void clk_gate_disable(struct stm32_clk_priv *priv, int id)
171 const struct clk_stm32 *clk = _clk_get(priv, id);
174 mmio_clrbits_32(priv->base + cfg->offset, BIT(cfg->bit_idx));
177 static bool clk_gate_is_enabled(struct stm32_clk_priv *priv, int id)
179 const struct clk_stm32 *clk = _clk_get(priv, id);
182 return ((mmio_read_32(priv->base + cfg->offset) & BIT(cfg->bit_idx)) != 0U);
191 void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id)
193 const struct gate_cfg *gate = &priv->gates[gate_id];
194 uintptr_t addr = priv->base + gate->offset;
203 int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id)
205 const struct gate_cfg *gate = &priv->gates[gate_id];
206 uintptr_t addr = priv->base + gate->offset;
218 const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id)
220 if ((unsigned int)id < priv->num) {
221 return &priv->clks[id];
269 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)
271 const struct parent_cfg *parents = &priv->parents[pid & MUX_PARENT_MASK];
273 uintptr_t address = priv->base + mux->offset;
298 int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int clk, int clkp)
305 pid = priv->clks[clk].parent;
311 old_parent = _clk_stm32_get_parent(priv, clk);
319 parents = &priv->parents[pid & MUX_PARENT_MASK];
323 bool clk_was_enabled = _clk_stm32_is_enabled(priv, clk);
327 _clk_stm32_enable(priv, clkp);
328 _clk_stm32_enable(priv, old_parent);
330 err = clk_mux_set_parent(priv, pid, sel);
332 _clk_stm32_disable(priv, old_parent);
335 _clk_stm32_disable(priv, old_parent);
337 _clk_stm32_disable(priv, clkp);
347 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id)
353 if (mux_id >= priv->nb_parents) {
357 parent = &priv->parents[mux_id];
362 return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift;
365 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel)
369 pid = priv->clks[clk].parent;
375 return clk_mux_set_parent(priv, pid, sel);
378 int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int clk_id)
380 const struct clk_stm32 *clk = _clk_get(priv, clk_id);
385 mux_id = priv->clks[clk_id].parent;
395 parent = &priv->parents[mux_id];
398 sel = clk->ops->get_parent(priv, clk_id);
400 sel = clk_mux_get_parent(priv, mux_id);
410 int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id)
414 mux_id = priv->clks[clk_id].parent;
425 return clk_mux_get_parent(priv, mux_id);
428 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx)
433 mux_id = priv->clks[clk_id].parent;
443 parent = &priv->parents[mux_id];
452 int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id)
456 for (i = 0U; i < priv->num; i++) {
457 if (binding_id == priv->clks[i].binding) {
465 unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id)
467 const struct clk_stm32 *clk = _clk_get(priv, id);
470 if ((unsigned int)id >= priv->num) {
474 parent = _clk_stm32_get_parent(priv, id);
483 prate = _clk_stm32_get_rate(priv, parent);
486 return clk->ops->recalc_rate(priv, id, prate);
493 return _clk_stm32_get_rate(priv, parent);
496 unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id)
498 int parent_id = _clk_stm32_get_parent(priv, id);
504 return _clk_stm32_get_rate(priv, parent_id);
507 static uint8_t _stm32_clk_get_flags(struct stm32_clk_priv *priv, int id)
509 return priv->clks[id].flags;
512 bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag)
514 if ((_stm32_clk_get_flags(priv, id) & flag) != 0U) {
521 int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
523 const struct clk_stm32 *clk = _clk_get(priv, id);
526 clk->ops->enable(priv, id);
532 static int _clk_stm32_enable_core(struct stm32_clk_priv *priv, int id)
537 if (priv->gate_refcounts[id] == 0U) {
538 parent = _clk_stm32_get_parent(priv, id);
543 ret = _clk_stm32_enable_core(priv, parent);
548 clk_stm32_enable_call_ops(priv, id);
551 priv->gate_refcounts[id]++;
553 if (priv->gate_refcounts[id] == UINT_MAX) {
561 int _clk_stm32_enable(struct stm32_clk_priv *priv, int id)
566 ret = _clk_stm32_enable_core(priv, id);
572 void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id)
574 const struct clk_stm32 *clk = _clk_get(priv, id);
577 clk->ops->disable(priv, id);
581 static void _clk_stm32_disable_core(struct stm32_clk_priv *priv, int id)
585 if ((priv->gate_refcounts[id] == 1U) && _stm32_clk_is_flags(priv, id, CLK_IS_CRITICAL)) {
589 if (priv->gate_refcounts[id] == 0U) {
591 if (_clk_stm32_is_enabled(priv, id)) {
592 clk_stm32_disable_call_ops(priv, id);
599 if (--priv->gate_refcounts[id] > 0U) {
603 clk_stm32_disable_call_ops(priv, id);
605 parent = _clk_stm32_get_parent(priv, id);
607 _clk_stm32_disable_core(priv, parent);
611 void _clk_stm32_disable(struct stm32_clk_priv *priv, int id)
615 _clk_stm32_disable_core(priv, id);
620 bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id)
622 const struct clk_stm32 *clk = _clk_get(priv, id);
625 return clk->ops->is_enabled(priv, id);
628 return priv->gate_refcounts[id];
633 struct stm32_clk_priv *priv = clk_stm32_get_priv();
636 id = clk_get_index(priv, binding_id);
641 return _clk_stm32_enable(priv, id);
646 struct stm32_clk_priv *priv = clk_stm32_get_priv();
649 id = clk_get_index(priv, binding_id);
651 _clk_stm32_disable(priv, id);
657 struct stm32_clk_priv *priv = clk_stm32_get_priv();
660 id = clk_get_index(priv, binding_id);
665 return _clk_stm32_is_enabled(priv, id);
670 struct stm32_clk_priv *priv = clk_stm32_get_priv();
673 id = clk_get_index(priv, binding_id);
678 return _clk_stm32_get_rate(priv, id);
683 struct stm32_clk_priv *priv = clk_stm32_get_priv();
686 id = clk_get_index(priv, binding_id);
691 return _clk_stm32_get_parent(priv, id);
704 struct stm32_clk_priv *priv = clk_stm32_get_priv();
707 for (i = 0U; i < priv->num; i++) {
708 if (_stm32_clk_is_flags(priv, i, CLK_IS_CRITICAL)) {
709 _clk_stm32_enable(priv, i);
719 uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id)
721 const struct div_cfg *divider = &priv->div[div_id];
724 val = mmio_read_32(priv->base + divider->offset) >> divider->shift;
730 unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv,
734 const struct div_cfg *divider = &priv->div[div_id];
735 uint32_t val = clk_stm32_div_get_value(priv, div_id);
746 unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int id,
749 const struct clk_stm32 *clk = _clk_get(priv, id);
752 return _clk_stm32_divider_recalc(priv, div_cfg->id, prate);
759 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value)
766 if (div_id >= priv->nb_div) {
770 divider = &priv->div[div_id];
771 address = priv->base + divider->offset;
792 int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id,
795 const struct gate_cfg *gate = &priv->gates[gate_id];
796 uintptr_t address = priv->base + gate->offset;
822 int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int id)
824 const struct clk_stm32 *clk = _clk_get(priv, id);
826 const struct gate_cfg *gate = &priv->gates[cfg->id];
827 uintptr_t addr = priv->base + gate->offset;
839 void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int id)
841 const struct clk_stm32 *clk = _clk_get(priv, id);
843 const struct gate_cfg *gate = &priv->gates[cfg->id];
844 uintptr_t addr = priv->base + gate->offset;
853 bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id)
858 gate = &priv->gates[gate_id];
859 addr = priv->base + gate->offset;
864 bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int id)
866 const struct clk_stm32 *clk = _clk_get(priv, id);
869 return _clk_stm32_gate_is_enabled(priv, cfg->id);
882 unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv,
885 const struct clk_stm32 *clk = _clk_get(priv, id);
902 static unsigned long timer_recalc_rate(struct stm32_clk_priv *priv,
905 const struct clk_stm32 *clk = _clk_get(priv, id);
908 uintptr_t rcc_base = priv->base;
927 static unsigned long clk_fixed_rate_recalc(struct stm32_clk_priv *priv, int id,
930 const struct clk_stm32 *clk = _clk_get(priv, id);
940 static unsigned long clk_stm32_osc_recalc_rate(struct stm32_clk_priv *priv,
943 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
948 bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id)
950 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
952 return _clk_stm32_gate_is_enabled(priv, osc_data->gate_id);
956 int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id)
958 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
960 _clk_stm32_gate_enable(priv, osc_data->gate_id);
962 if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, true) != 0U) {
970 void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id)
972 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
974 _clk_stm32_gate_disable(priv, osc_data->gate_id);
976 if (_clk_stm32_gate_wait_ready(priv, osc_data->gate_rdy_id, false) != 0U) {
1023 void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id)
1025 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, id);
1067 int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base)
1071 stm32_clock_data = priv;
1073 priv->base = base;
1075 for (i = 0U; i < priv->num; i++) {
1076 const struct clk_stm32 *clk = _clk_get(priv, i);
1081 clk->ops->init(priv, i);