Lines Matching defs:reg_base
50 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE)
73 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS);
81 mmio_write_32(reg_base + HC_HOSTSTATUS, status);
87 mmio_write_32(reg_base + HC_ARGUMENT, arg);
88 mmio_write_32(reg_base + HC_COMMAND, cmd | HC_CMD_ENABLE);
137 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) {
143 mmio_read_32(reg_base + HC_DATAPORT);
150 edm = mmio_read_32(reg_base + HC_DEBUG);
160 mmio_write_32(reg_base + HC_DEBUG,
178 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
181 mmio_read_32(reg_base + HC_COMMAND));
183 mmio_read_32(reg_base + HC_ARGUMENT));
185 mmio_read_32(reg_base + HC_TIMEOUTCOUNTER));
187 mmio_read_32(reg_base + HC_CLOCKDIVISOR));
189 mmio_read_32(reg_base + HC_RESPONSE_0));
191 mmio_read_32(reg_base + HC_RESPONSE_1));
193 mmio_read_32(reg_base + HC_RESPONSE_2));
195 mmio_read_32(reg_base + HC_RESPONSE_3));
197 mmio_read_32(reg_base + HC_HOSTSTATUS));
199 mmio_read_32(reg_base + HC_POWER));
201 mmio_read_32(reg_base + HC_DEBUG));
203 mmio_read_32(reg_base + HC_HOSTCONFIG));
205 mmio_read_32(reg_base + HC_BLOCKSIZE));
207 mmio_read_32(reg_base + HC_BLOCKCOUNT));
215 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
219 mmio_write_32(reg_base + HC_POWER, 0);
220 mmio_write_32(reg_base + HC_COMMAND, 0);
221 mmio_write_32(reg_base + HC_ARGUMENT, 0);
223 mmio_write_32(reg_base + HC_TIMEOUTCOUNTER, HC_TIMEOUT_DEFAULT);
224 mmio_write_32(reg_base + HC_CLOCKDIVISOR, 0);
225 mmio_write_32(reg_base + HC_HOSTSTATUS, HC_HSTST_RESET);
226 mmio_write_32(reg_base + HC_HOSTCONFIG, 0);
227 mmio_write_32(reg_base + HC_BLOCKSIZE, 0);
228 mmio_write_32(reg_base + HC_BLOCKCOUNT, 0);
230 dbg = mmio_read_32(reg_base + HC_DEBUG);
235 mmio_write_32(reg_base + HC_DEBUG, dbg);
237 mmio_write_32(reg_base + HC_POWER, 1);
241 mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_MAXVAL);
242 tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
243 mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1 | HC_HSTCF_INT_BUSY);
248 assert((rpi3_sdhost_params.reg_base & MMC_BLOCK_MASK) == 0);
259 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
341 intmask = mmio_read_32(reg_base + HC_HOSTSTATUS);
343 mmio_write_32(reg_base + HC_HOSTSTATUS, HC_HSTST_INT_BUSY);
353 cmd->resp_data[0] = mmio_read_32(reg_base + HC_RESPONSE_0);
354 cmd->resp_data[1] = mmio_read_32(reg_base + HC_RESPONSE_1);
355 cmd->resp_data[2] = mmio_read_32(reg_base + HC_RESPONSE_2);
356 cmd->resp_data[3] = mmio_read_32(reg_base + HC_RESPONSE_3);
358 if (mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_FAILED) {
359 uint32_t sdhsts = mmio_read_32(reg_base + HC_HOSTSTATUS);
361 mmio_write_32(reg_base + HC_HOSTSTATUS,
376 mmio_read_32(reg_base + HC_COMMAND));
394 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
399 mmio_write_32(reg_base + HC_CLOCKDIVISOR,
420 mmio_write_32(reg_base + HC_CLOCKDIVISOR, div);
426 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
438 tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
443 mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1);
444 tmp1 = mmio_read_32(reg_base + HC_HOSTCONFIG);
445 mmio_write_32(reg_base + HC_HOSTCONFIG, tmp1 |
453 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
469 mmio_write_32(reg_base + HC_BLOCKSIZE, blocksize);
470 mmio_write_32(reg_base + HC_BLOCKCOUNT, blocks);
479 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
487 while ((mmio_read_32(reg_base + HC_HOSTSTATUS)
501 uint32_t data = mmio_read_32(reg_base + HC_DATAPORT);
503 hsts_err = mmio_read_32(reg_base + HC_HOSTSTATUS)
508 mmio_read_32(reg_base + HC_HOSTSTATUS));
514 mmio_write_32(reg_base + HC_HOSTSTATUS, hsts_err);
521 remaining_words = (mmio_read_32(reg_base + HC_DEBUG) >> 4)
543 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
553 mmio_write_32(reg_base + HC_DATAPORT, data);
555 dbg = mmio_read_32(reg_base + HC_DEBUG);
563 hsts_err = mmio_read_32(reg_base + HC_HOSTSTATUS)
570 remaining_words = (mmio_read_32(reg_base + HC_DEBUG) >> 4)
592 ((params->reg_base & MMC_BLOCK_MASK) == 0));
631 uintptr_t reg_base = rpi3_sdhost_params.reg_base;
637 mmio_write_32(reg_base+HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_SLOWVAL);
644 mmio_write_32(reg_base + HC_COMMAND, 0);
645 mmio_write_32(reg_base + HC_ARGUMENT, 0);
646 mmio_write_32(reg_base + HC_TIMEOUTCOUNTER, HC_TIMEOUT_IDLE);
647 mmio_write_32(reg_base + HC_CLOCKDIVISOR, HC_CLOCKDIVISOR_STOPVAL);
651 mmio_write_32(reg_base + HC_POWER, 0);
652 mmio_write_32(reg_base + HC_HOSTCONFIG, 0);
653 mmio_write_32(reg_base + HC_BLOCKSIZE, 0x400);
654 mmio_write_32(reg_base + HC_BLOCKCOUNT, 0);
655 mmio_write_32(reg_base + HC_HOSTSTATUS, 0x7f8);
657 mmio_write_32(reg_base + HC_COMMAND, 0);
658 mmio_write_32(reg_base + HC_ARGUMENT, 0);