Lines Matching defs:slice
246 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
248 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
250 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
678 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
689 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
702 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
712 adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
731 static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
736 ddr_setval_s(ch, slice, regdef, val);
746 uint32_t slice;
748 for (slice = 0; slice < SLICE_CNT; slice++)
749 ddr_setval_ach_s(slice, regdef, val);
768 uint32_t ch, slice;
773 for (slice = 0; slice < SLICE_CNT; slice++)
774 *pp++ = ddr_getval_s(ch, slice, regdef);
1240 uint32_t slice;
1534 for (slice = 0; slice < SLICE_CNT; slice++) {
1537 DDR_PHY_SLICE_REGSET_SIZE * slice;
1578 for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
1581 DDR_PHY_ADR_I_REGSET_SIZE * slice;
1607 uint32_t ch, slice;
1615 for (slice = 0; slice < SLICE_CNT; slice++) {
1616 high_byte[slice] =
1617 (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
1618 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
1619 board_cnf->ch[ch].dq_swap[slice]);
1620 ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
1621 board_cnf->ch[ch].dm_swap[slice]);
1622 if (high_byte[slice]) {
1624 ddr_setval_s(ch, slice,
1629 ddr_setval_s(ch, slice,
1743 uint32_t slice;
1753 for (slice = 0; slice < SLICE_CNT; slice++) {
1754 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
1759 if (slice % 2)
1766 uint32_t ch, slice;
1786 for (slice = 0; slice < SLICE_CNT; slice++) {
1787 tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
1789 high_byte[slice] = tmp % 2;
1790 if (tmp == 1 && (slice >= 2))
1792 if (tmp == 3 && (slice >= 2))
1794 ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
1795 board_cnf->ch[ch].dq_swap[slice]);
1796 if (high_byte[slice]) {
1798 ddr_setval_s(ch, slice,
1803 ddr_setval_s(ch, slice,
1821 for (slice = 0; slice < SLICE_CNT; slice++) {
1822 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
1824 ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
1827 if (high_byte[slice])
1832 tmp = board_cnf->ch[ch].dq_swap[slice];
1842 if (!high_byte[slice])
1844 if (high_byte[slice])
1846 ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
1855 uint32_t ch, slice;
1876 for (slice = 0; slice < SLICE_CNT; slice++) {
1884 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
1886 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
1888 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
1890 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
1892 ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
1958 for (slice = 0; slice < SLICE_CNT; slice++) {
1960 dq = slice * 8 + i;
1962 _adj = board_cnf->ch[ch].dm_adj_w[slice];
1966 ddr_setval_s(ch, slice,
1976 for (slice = 0; slice < SLICE_CNT; slice++) {
1978 dq = slice * 8 + i;
1980 _adj = board_cnf->ch[ch].dm_adj_r[slice];
1984 ddr_setval_s(ch, slice,
1987 ddr_setval_s(ch, slice,
2347 uint32_t slice, rdlat_max, rdlat_min;
2354 for (slice = 0; slice < SLICE_CNT; slice++) {
2355 ddr_setval_s(ch, slice,
2358 data_l = ddr_getval_s(ch, slice,
2987 uint32_t ch, slice;
3123 for (slice = 0; slice < SLICE_CNT; slice++) {
3124 ddr_setval_s(ch, slice,
3268 uint32_t cs, slice;
3274 for (slice = 0; slice < SLICE_CNT; slice++) {
3275 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3281 wdqdm_dly[ch][cs][slice][i] =
3282 wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
3284 wdqdm_dly[ch][cs][slice][i] = data_l;
3285 wdqdm_le[ch][cs][slice][i] = 0;
3286 wdqdm_te[ch][cs][slice][i] = 0;
3288 wdqdm_st[ch][cs][slice] = 0;
3289 wdqdm_win[ch][cs][slice] = 0;
3296 uint32_t cs, slice;
3309 for (slice = 0; slice < SLICE_CNT; slice += 1) {
3310 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3315 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
3317 dq = slice * 8 + i;
3319 _adj = board_cnf->ch[ch].dm_adj_w[slice];
3325 ddr_getval_s(ch, slice,
3327 ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
3329 wdqdm_dly[ch][cs][slice][i] = data_l;
3331 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
3332 data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
3333 wdqdm_st[ch][cs][slice] = data_l;
3336 ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
3340 ddr_getval_s(ch, slice,
3342 wdqdm_te[ch][cs][slice][i] = data_l;
3344 ddr_getval_s(ch, slice,
3346 wdqdm_le[ch][cs][slice][i] = data_l;
3348 (int32_t)wdqdm_te[ch][cs][slice][i] -
3349 wdqdm_le[ch][cs][slice][i];
3355 wdqdm_win[ch][cs][slice] = min_win;
3358 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
3361 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
3372 uint32_t ch, slice;
3379 for (slice = 0; slice < SLICE_CNT; slice++) {
3380 ddr_setval_s(ch, slice,
3389 rdqdm_dly[ch][tgt_cs][slice]
3393 rdqdm_dly[ch][src_cs][slice]
3396 ddr_setval_s(ch, slice,
3408 uint32_t ch, cs, slice;
3422 for (slice = 0; slice < SLICE_CNT; slice++) {
3424 (4 * slice)) & 0x0f;
3426 high_dq[ch] |= (1U << slice);
3644 uint32_t cs, slice;
3650 for (slice = 0; slice < SLICE_CNT; slice++) {
3651 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3657 rdqdm_dly[ch][cs][slice][i] =
3658 rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
3659 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
3660 rdqdm_dly[ch][CS_CNT - 1 - cs][slice +
3664 rdqdm_dly[ch][cs][slice][i] = data_l;
3665 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
3668 rdqdm_le[ch][cs][slice][i] = 0;
3669 rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
3670 rdqdm_te[ch][cs][slice][i] = 0;
3671 rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0;
3672 rdqdm_nw[ch][cs][slice][i] = 0;
3673 rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0;
3675 rdqdm_st[ch][cs][slice] = 0;
3676 rdqdm_win[ch][cs][slice] = 0;
3683 uint32_t cs, slice;
3695 for (slice = 0; slice < SLICE_CNT; slice++) {
3696 k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
3701 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
3704 ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
3708 dq = slice * 8 + i;
3710 _adj = board_cnf->ch[ch].dm_adj_r[slice];
3717 ddr_getval_s(ch, slice,
3720 ddr_setval_s(ch, slice,
3723 rdqdm_dly[ch][cs][slice][i] = data_l;
3726 ddr_getval_s(ch, slice,
3729 ddr_setval_s(ch, slice,
3732 rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
3737 ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
3738 rdqdm_st[ch][cs][slice] = data_l;
3739 rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
3747 ddr_setval_s(ch, slice,
3752 ddr_getval_s(ch, slice,
3754 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
3758 ddr_getval_s(ch, slice,
3760 rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
3764 ddr_getval_s(ch, slice,
3766 rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
3770 (int32_t)rdqdm_te[ch][cs][slice +
3773 rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
3780 rdqdm_win[ch][cs][slice] = min_win;
3794 uint32_t slice;
3822 for (slice = 0; slice < SLICE_CNT; slice++) {
3823 if (ddr_getval_s(ch, slice,
3827 (0x10U << slice);
3836 for (slice = 0; slice < SLICE_CNT; slice++) {
3839 adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
3841 adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
3842 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
3843 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
3844 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
3845 rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
3846 rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
3848 data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
3849 ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
3850 rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
3851 rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
3962 uint32_t ch, slice;
3971 for (slice = 0; slice < SLICE_CNT; slice++) {
3973 val[ch][slice][index] = 0;
3986 for (slice = 0; slice < SLICE_CNT; slice++) {
3987 tmp = tmp_ach_as[ch][slice];
3991 val[ch][slice][index] |=
3994 val[ch][slice][index] &=
4002 for (slice = 0; slice < SLICE_CNT; slice++) {
4005 tmpval = val[ch][slice][index];
4013 ddr_setval_s(ch, slice,
4025 uint32_t ch, slice;
4041 for (slice = 0; slice < SLICE_CNT; slice++)
4042 tmp_ach_as[ch][slice] =
4043 ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
4047 for (slice = 0; slice < SLICE_CNT; slice++) {
4048 tmp = tmp_ach_as[ch][slice];
4074 uint32_t ch, slice;
4082 for (slice = 0; slice < SLICE_CNT; slice++) {
4083 ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX,
4087 ddr_getval_s(ch, slice,
4090 ddr_getval_s(ch, slice,
4094 rdlat_adjx2[slice] = tmp;
4099 for (slice = 0; slice < SLICE_CNT; slice++) {
4100 tmp = maxlatx2 - rdlat_adjx2[slice];
4103 ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE,
4104 ddr_getval_s(ch, slice,
4115 uint32_t ch, cs, slice;
4121 for (slice = 0; slice < SLICE_CNT; slice += 1) {
4123 ddr_setval_s(ch, slice,
4126 ddr_getval_s(ch, slice,
4129 ddr_getval_s(ch, slice,
4135 ddr_getval_s(ch, slice,
4137 ddr_setval_s(ch, slice,