Lines Matching defs:tzc380_reg_list

64  *	tzc380_reg_list	: TZC380 Region List
76 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
85 		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
86 		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
87 		tzc380_reg_list[list_idx].addr = UL(0x0);
88 		tzc380_reg_list[list_idx].size = 0x0;
89 		tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
98 		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
99 		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
100 		tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
101 		tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_2M;
102 		tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
109 		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
110 		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
111 		tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + shrd_dram_sz;
112 		tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_64M;
113 		tzc380_reg_list[list_idx].sub_mask = 0x80; /* Disable sub-region 7 */
120 		tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
121 		tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
122 		tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
123 		tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_8M;
124 		tzc380_reg_list[list_idx].sub_mask = 0xC0; /* Disable sub-region 6 & 7 */
132 int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
139 	ERROR("tzc380_reg_list used is not a default list\n");
147 			struct tzc380_reg *tzc380_reg_list)
159 		attr_value = tzc380_reg_list[indx].secure |
160 			TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) |
161 			TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) |
162 			tzc380_reg_list[indx].enabled;
164 		tzc380_configure_region(indx, tzc380_reg_list[indx].addr,