Lines Matching defs:list_idx
66 * list_idx : TZC380 Region List Index
73 * list_idx : last populated index + 1
77 int dram_idx, int list_idx,
84 if (list_idx == 0) {
85 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
86 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
87 tzc380_reg_list[list_idx].addr = UL(0x0);
88 tzc380_reg_list[list_idx].size = 0x0;
89 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
90 list_idx++;
98 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
99 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
100 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
101 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_2M;
102 tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
103 list_idx++;
109 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
110 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
111 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + shrd_dram_sz;
112 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_64M;
113 tzc380_reg_list[list_idx].sub_mask = 0x80; /* Disable sub-region 7 */
114 list_idx++;
120 tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
121 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
122 tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
123 tzc380_reg_list[list_idx].size = TZC_REGION_SIZE_8M;
124 tzc380_reg_list[list_idx].sub_mask = 0xC0; /* Disable sub-region 6 & 7 */
125 list_idx++;
129 return list_idx;
133 int dram_idx, int list_idx,