Lines Matching defs:uint32_t
37 static uint32_t map_phy_addr_space(uint32_t addr)
40 uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */
41 uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */
42 uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */
43 uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */
70 static inline uint16_t *phy_io_addr(void *phy, uint32_t addr)
75 static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data)
83 static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr)
99 static void read_phy_reg(uint16_t *phy, uint32_t addr,
100 uint16_t *buf, uint32_t len)
102 uint32_t i = 0U;
109 static uint32_t findrank(uint32_t cs_in_use)
111 uint32_t val = 0U;
129 static uint8_t findmax(uint8_t *buf, uint32_t len)
132 uint32_t i = 0U;
143 static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
144 uint32_t *tcfg0, uint32_t *tcfg4)
147 uint32_t i, val = 0U;
373 int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
374 uint32_t num_of_phy, int train2d
382 uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
469 int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
470 uint32_t num_of_phy, int train2d
477 uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
504 ret = xspi_read(phy_store, (uint32_t *)training_1D_values,
532 (uint32_t *)training_2D_values, size);
559 ret = xspi_read(phy_store, (uint32_t *)ddrctrl_regs, size);
614 uint32_t f0rc0a;
615 uint32_t f0rc3x;
616 uint32_t f0rc5x;
661 uint32_t addr;
677 uint32_t addr;
1029 uint32_t addr;
1056 uint32_t addr;
1091 uint32_t addr = t_master | csr_enable_cs_multicast_addr;
1174 uint32_t addr;
1199 uint32_t addr = t_master | csr_pll_ctrl2_addr;
1224 uint32_t addr = t_master | csr_dll_lockparam_addr;
1232 uint32_t addr = t_master | csr_dll_gain_ctl_addr;
1241 uint32_t addr;
1253 uint32_t addr = t_master | csr_ard_ptr_init_val_addr;
1268 uint32_t addr = t_master | csr_dqs_preamble_control_addr;
1296 uint32_t addr = t_master | csr_proc_odt_time_ctl_addr;
1388 uint32_t addr;
1463 uint32_t addr;
1562 uint32_t addr;
1587 uint32_t addr;
1600 uint32_t addr;
1611 uint32_t addr = t_master | csr_dfi_camode_addr;
1622 uint32_t addr;
1636 uint32_t addr;
1653 uint32_t addr;
1670 uint32_t addr;
1695 uint32_t addr;
1728 uint32_t addr;
1754 uint32_t addr = t_master | csr_dfi_freq_ratio_addr;
1767 uint32_t addr = t_master | csr_tristate_mode_ca_addr;
1783 uint32_t addr;
1808 uint32_t addr;
1841 uint32_t addr = t_master | csr_master_x4config_addr;
1853 uint32_t addr = t_master | csr_dmipin_present_addr;
1863 uint32_t addr;
1876 uint32_t addr;
1954 static uint32_t get_mail(uint16_t *phy, int stream)
1957 uint32_t mail = 0U;
1997 static const char *lookup_msg(uint32_t index, int train2d)
2025 uint32_t index __unused;
2028 __unused uint32_t args[MAX_ARGS];
2056 uint32_t mail = 0U;
2184 uint32_t dst,
2186 uint32_t size)
2188 uint32_t i;
2208 int (*img_loadr)(unsigned int, uintptr_t *, uint32_t *),
2209 uint32_t warm_boot_flag)
2211 uint32_t imem_id, dmem_id;
2213 uint32_t size;