Lines Matching defs:phy
29 #include "phy.h"
70 static inline uint16_t *phy_io_addr(void *phy, uint32_t addr)
72 return phy + (map_phy_addr_space(addr) << 2);
75 static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data)
77 mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data);
83 static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr)
85 uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr));
99 static void read_phy_reg(uint16_t *phy, uint32_t addr,
105 buf[i] = phy_io_read16(phy, (addr + i));
148 uint16_t *phy;
157 phy = phy_ptr[i];
158 if (phy == NULL) {
162 phy_io_write16(phy, t_apbonly |
165 read_phy_reg(phy, CDD_VAL_READ_ADDR,
168 phy_io_write16(phy, t_apbonly |
381 uint16_t *phy = NULL, value = 0x0;
392 phy = phy_ptr[j];
397 phy_io_write16(phy, t_apbonly |
400 phy_io_write16(phy, t_drtub |
415 value = phy_io_read16(phy, training_1D_values[i].addr);
419 phy_io_addr(phy,
432 value = phy_io_read16(phy,
438 value, phy_io_addr(phy,
456 phy_io_write16(phy, t_drtub |
459 phy_io_write16(phy, t_apbonly |
476 uint16_t *phy = NULL;
482 phy = phy_ptr[j];
497 phy_io_write16(phy, t_apbonly |
500 phy_io_write16(phy, t_drtub |
516 phy_io_write16(phy, training_1D_values[i].addr,
522 phy_io_addr(phy,
545 phy_io_write16(phy, training_2D_values[i].addr,
551 phy_io_addr(phy,
562 phy_io_write16(phy, t_drtub |
565 phy_io_write16(phy, t_apbonly |
575 static void load_pieimage(uint16_t *phy,
604 phy_io_write16(phy, image[i].addr, image[i].data);
608 static void prog_acsm_playback(uint16_t *phy,
634 phy_io_write16(phy, t_acsm | (csr_acsm_playback0x0_addr +
636 phy_io_write16(phy, t_acsm | (csr_acsm_playback1x0_addr +
641 static void prog_acsm_ctr(uint16_t *phy,
648 phy_io_write16(phy, t_acsm | csr_acsm_ctrl13_addr,
651 phy_io_write16(phy, t_acsm | csr_acsm_ctrl0_addr,
655 static void prog_cal_rate_run(uint16_t *phy,
669 phy_io_write16(phy, addr, cal_rate);
672 static void prog_seq0bdly0(uint16_t *phy,
711 phy_io_write16(phy, addr, ps_count[0]);
713 debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr));
716 phy_io_write16(phy, addr, ps_count[1]);
718 debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr));
721 phy_io_write16(phy, addr, ps_count[2]);
723 debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr));
726 phy_io_write16(phy, addr, ps_count[3]);
728 debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr));
737 uint16_t *phy;
740 phy = phy_ptr[i];
741 if (phy == NULL) {
745 phy_io_write16(phy,
749 load_pieimage(phy, input->basic.dimm_type);
751 prog_seq0bdly0(phy, input);
752 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag0_addr,
754 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag1_addr,
756 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag2_addr,
758 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag3_addr,
760 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag4_addr,
762 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag5_addr,
764 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag6_addr,
768 phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag7_addr,
770 prog_acsm_playback(phy, input, msg); /* rdimm */
771 prog_acsm_ctr(phy, input); /* rdimm */
773 phy_io_write16(phy, t_master | csr_cal_zap_addr, U(0x1));
774 prog_cal_rate_run(phy, input);
776 phy_io_write16(phy, t_drtub | csr_ucclk_hclk_enables_addr,
779 phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 1U);
1023 static void prog_tx_pre_drv_mode(uint16_t *phy,
1045 phy_io_write16(phy, addr, tx_slew_rate);
1050 static void prog_atx_pre_drv_mode(uint16_t *phy,
1084 phy_io_write16(phy, addr, atx_slew_rate);
1088 static void prog_enable_cs_multicast(uint16_t *phy,
1098 phy_io_write16(phy, addr, input->adv.cast_cs_to_cid);
1101 static void prog_dfi_rd_data_cs_dest_map(uint16_t *phy,
1119 phy_io_write16(phy,
1136 phy_io_write16(phy,
1139 phy_io_write16(phy,
1160 phy_io_write16(phy, t_master | csr_dfi_rd_data_cs_dest_map_addr,
1162 phy_io_write16(phy, t_master | csr_dfi_wr_data_cs_dest_map_addr,
1171 static void prog_pll_ctrl(uint16_t *phy,
1180 phy_io_write16(phy, addr, pll_ctrl1);
1182 debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr));
1185 phy_io_write16(phy, addr, pll_test_mode);
1187 debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr));
1190 phy_io_write16(phy, addr, pll_ctrl4);
1192 debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr));
1195 static void prog_pll_ctrl2(uint16_t *phy,
1217 phy_io_write16(phy, addr, pll_ctrl2);
1219 debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr));
1222 static void prog_dll_lck_param(uint16_t *phy, const struct input *input)
1226 phy_io_write16(phy, addr, U(0x212));
1227 debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr));
1230 static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input)
1234 phy_io_write16(phy, addr, U(0x61));
1235 debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr));
1238 static void prog_pll_pwr_dn(uint16_t *phy,
1244 phy_io_write16(phy, addr, 0U);
1246 debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr));
1249 static void prog_ard_ptr_init_val(uint16_t *phy,
1261 phy_io_write16(phy, addr, ard_ptr_init_val);
1264 static void prog_dqs_preamble_control(uint16_t *phy,
1285 phy_io_write16(phy, addr, data);
1289 phy_io_write16(phy, addr, data);
1292 static void prog_proc_odt_time_ctl(uint16_t *phy,
1315 phy_io_write16(phy, addr, proc_odt_time_ctl);
1382 static void prog_tx_odt_drv_stren(uint16_t *phy,
1404 phy_io_write16(phy, addr, tx_odt_drv_stren);
1457 static void prog_tx_impedance_ctrl1(uint16_t *phy,
1478 phy_io_write16(phy, addr, tx_impedance_ctrl1);
1555 static void prog_atx_impedance(uint16_t *phy,
1579 phy_io_write16(phy, addr, atx_impedance);
1583 static void prog_dfi_mode(uint16_t *phy,
1595 phy_io_write16(phy, addr, dfi_mode);
1598 static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input)
1603 phy_io_write16(phy, addr, 0x0);
1604 debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr));
1607 static void prog_dfi_camode(uint16_t *phy,
1613 phy_io_write16(phy, addr, dfi_camode);
1616 static void prog_cal_drv_str0(uint16_t *phy,
1629 phy_io_write16(phy, addr, cal_drv_str0);
1632 static void prog_cal_uclk_info(uint16_t *phy,
1644 phy_io_write16(phy, addr, cal_uclk_ticks_per1u_s);
1647 static void prog_cal_rate(uint16_t *phy,
1660 phy_io_write16(phy, addr, cal_rate);
1663 static void prog_vref_in_global(uint16_t *phy,
1682 phy_io_write16(phy, addr, vref_in_global);
1685 static void prog_dq_dqs_rcv_cntrl(uint16_t *phy,
1712 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl);
1717 static void prog_mem_alert_control(uint16_t *phy,
1744 phy_io_write16(phy, addr, mem_alert_control);
1746 phy_io_write16(phy, addr, mem_alert_control2);
1750 static void prog_dfi_freq_ratio(uint16_t *phy,
1757 phy_io_write16(phy, addr, dfi_freq_ratio);
1760 static void prog_tristate_mode_ca(uint16_t *phy,
1774 phy_io_write16(phy, addr, tristate_mode_ca);
1777 static void prog_dfi_xlat(uint16_t *phy,
1796 phy_io_write16(phy, addr, dfifreqxlat_dat);
1800 static void prog_dbyte_misc_mode(uint16_t *phy,
1825 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1_1);
1829 phy_io_write16(phy, addr, dbyte_misc_mode);
1831 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1);
1836 static void prog_master_x4config(uint16_t *phy,
1845 phy_io_write16(phy, addr, master_x4config);
1848 static void prog_dmipin_present(uint16_t *phy,
1856 phy_io_write16(phy, addr, dmipin_present);
1859 static void prog_dfi_phyupd(uint16_t *phy,
1866 dfiphyupd_dat = phy_io_read16(phy, addr) &
1869 phy_io_write16(phy, addr, dfiphyupd_dat);
1872 static void prog_cal_misc2(uint16_t *phy,
1879 cal_misc2_dat = phy_io_read16(phy, addr) |
1882 phy_io_write16(phy, addr, cal_misc2_dat);
1887 cal_offsets_dat = (phy_io_read16(phy, addr) & ~csr_cal_drv_pdth_mask)
1890 phy_io_write16(phy, addr, cal_offsets_dat);
1899 uint16_t *phy;
1903 phy = phy_ptr[i];
1904 if (phy == NULL) {
1909 prog_dfi_phyupd(phy, input);
1910 prog_cal_misc2(phy, input);
1911 prog_tx_pre_drv_mode(phy, input);
1912 prog_atx_pre_drv_mode(phy, input);
1913 prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */
1914 prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg);
1915 prog_pll_ctrl2(phy, input);
1920 prog_pll_pwr_dn(phy, input);
1923 phy_io_write16(phy, 0x010048, 0x1);
1926 prog_ard_ptr_init_val(phy, input);
1927 prog_dqs_preamble_control(phy, input);
1928 prog_dll_lck_param(phy, input);
1929 prog_dll_gain_ctl(phy, input);
1930 prog_proc_odt_time_ctl(phy, input);
1931 prog_tx_odt_drv_stren(phy, input);
1932 prog_tx_impedance_ctrl1(phy, input);
1933 prog_atx_impedance(phy, input);
1934 prog_dfi_mode(phy, input);
1935 prog_dfi_camode(phy, input);
1936 prog_cal_drv_str0(phy, input);
1937 prog_cal_uclk_info(phy, input);
1938 prog_cal_rate(phy, input);
1939 prog_vref_in_global(phy, input, msg);
1940 prog_dq_dqs_rcv_cntrl(phy, input);
1941 prog_mem_alert_control(phy, input);
1942 prog_dfi_freq_ratio(phy, input);
1943 prog_tristate_mode_ca(phy, input);
1944 prog_dfi_xlat(phy, input);
1945 prog_dbyte_misc_mode(phy, input, msg);
1946 prog_master_x4config(phy, input);
1947 prog_dmipin_present(phy, input, msg);
1948 prog_acx4_anib_dis(phy, input);
1954 static uint32_t get_mail(uint16_t *phy, int stream)
1961 ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
1970 mail = phy_io_read16(phy, t_apbonly |
1973 mail |= phy_io_read16(phy, t_apbonly |
1978 phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 0);
1982 ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
1991 phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 1U);
2023 static void decode_stream_message(uint16_t *phy, int train2d)
2032 index = get_mail(phy, 1);
2037 args[i] = get_mail(phy, 1);
2054 static int wait_fw_done(uint16_t *phy, int train2d)
2059 mail = get_mail(phy, 0);
2096 decode_stream_message(phy, train2d);
2150 uint16_t *phy;
2153 phy = phy_ptr[i];
2154 if (phy == NULL) {
2158 prog_pll_ctrl2(phy, input);
2159 prog_pll_ctrl(phy, input);
2160 phy_io_write16(phy,
2163 phy_io_write16(phy,
2167 phy_io_write16(phy,
2170 phy_io_write16(phy,
2174 ret = wait_fw_done(phy, train2d);
2183 static inline int send_fw(uint16_t *phy,
2196 phy_io_write16(phy, dst + i, *(img + i));
2216 uint16_t *phy;
2249 phy = phy_ptr[i];
2250 if (phy == NULL) {
2256 phy_io_write16(phy, t_master |
2262 phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 0);
2264 ret = send_fw(phy, PHY_GEN2_IMEM_ADDR,
2284 phy = phy_ptr[i];
2285 if (phy == NULL) {
2289 ret = send_fw(phy, PHY_GEN2_DMEM_ADDR, msg, len);
2294 ret = send_fw(phy, PHY_GEN2_DMEM_ADDR + len / 2,
2592 ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d);
2602 ret = restore_phy_training_values(priv->phy,
2631 ret = load_fw(priv->phy, &input, 0, &msg_1d,
2640 ret = g_exec_fw(priv->phy, 0, &input);
2651 get_cdd_val(priv->phy, rank, input.basic.frequency,
2661 ret = load_fw(priv->phy, &input, 1, &msg_2d,
2670 ret = g_exec_fw(priv->phy, 1, &input);
2684 debug("save the phy training data\n");
2686 ret = save_phy_training_values(priv->phy,
2704 i_load_pie(priv->phy, &input, &msg_1d);