Lines Matching defs:msg_blk
612 const struct ddr4r1d *msg_blk;
622 msg_blk = msg;
623 f0rc0a = (msg_blk->f0rc0a_d0 & U(0xf)) | U(0xa0);
624 f0rc3x = (msg_blk->f0rc3x_d0 & U(0xff)) | U(0x300);
731 /* Only RDIMM requires msg_blk */
837 struct ddr4u1d *msg_blk = msg_1d;
846 msg_blk->dram_type = U(0x2);
849 msg_blk->dram_type = U(0x4);
852 msg_blk->dram_type = U(0x5);
858 msg_blk->pstate = 0U;
861 msg_blk->reserved00 = U(0x20);
864 msg_blk->reserved00 |= U(0x40);
867 msg_blk->reserved1c[3] = U(0x3);
870 msg_blk->sequence_ctrl = U(0x3f1f);
872 msg_blk->sequence_ctrl = U(0x031f);
874 msg_blk->phy_config_override = 0U;
876 msg_blk->hdt_ctrl = U(0x5);
878 msg_blk->hdt_ctrl = U(0xc9);
880 msg_blk->msg_misc = U(0x0);
881 msg_blk->dfimrlmargin = U(0x1);
882 msg_blk->phy_vref = input->vref ? input->vref : U(0x61);
883 msg_blk->cs_present = input->cs_d0 | input->cs_d1;
884 msg_blk->cs_present_d0 = input->cs_d0;
885 msg_blk->cs_present_d1 = input->cs_d1;
887 msg_blk->addr_mirror = U(0x0a); /* odd CS are mirrored */
889 msg_blk->share2dvref_result = 1U;
891 msg_blk->acsm_odt_ctrl0 = input->odt[0];
892 msg_blk->acsm_odt_ctrl1 = input->odt[1];
893 msg_blk->acsm_odt_ctrl2 = input->odt[2];
894 msg_blk->acsm_odt_ctrl3 = input->odt[3];
895 msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 +
897 msg_blk->x16present = input->basic.dram_data_width == 0x10 ?
898 msg_blk->cs_present : 0;
899 msg_blk->d4misc = U(0x1);
900 msg_blk->cs_setup_gddec = U(0x1);
901 msg_blk->rtt_nom_wr_park0 = 0U;
902 msg_blk->rtt_nom_wr_park1 = 0U;
903 msg_blk->rtt_nom_wr_park2 = 0U;
904 msg_blk->rtt_nom_wr_park3 = 0U;
905 msg_blk->rtt_nom_wr_park4 = 0U;
906 msg_blk->rtt_nom_wr_park5 = 0U;
907 msg_blk->rtt_nom_wr_park6 = 0U;
908 msg_blk->rtt_nom_wr_park7 = 0U;
909 msg_blk->mr0 = input->mr[0];
910 msg_blk->mr1 = input->mr[1];
911 msg_blk->mr2 = input->mr[2];
912 msg_blk->mr3 = input->mr[3];
913 msg_blk->mr4 = input->mr[4];
914 msg_blk->mr5 = input->mr[5];
915 msg_blk->mr6 = input->mr[6];
916 if ((msg_blk->mr4 & U(0x1c0)) != 0U) {
920 msg_blk->alt_cas_l = 0U;
921 msg_blk->alt_wcas_l = 0U;
923 msg_blk->dramfreq = input->basic.frequency * 2U;
924 msg_blk->pll_bypass_en = input->basic.pll_bypass;
925 msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U :
928 msg_blk->bpznres_val = input->adv.ext_cal_res_val;
929 msg_blk->disabled_dbyte = 0U;
931 debug("msg_blk->dram_type = 0x%x\n", msg_blk->dram_type);
932 debug("msg_blk->sequence_ctrl = 0x%x\n", msg_blk->sequence_ctrl);
933 debug("msg_blk->phy_cfg = 0x%x\n", msg_blk->phy_cfg);
934 debug("msg_blk->x16present = 0x%x\n", msg_blk->x16present);
935 debug("msg_blk->dramfreq = 0x%x\n", msg_blk->dramfreq);
936 debug("msg_blk->pll_bypass_en = 0x%x\n", msg_blk->pll_bypass_en);
937 debug("msg_blk->dfi_freq_ratio = 0x%x\n", msg_blk->dfi_freq_ratio);
938 debug("msg_blk->phy_odt_impedance = 0x%x\n",
939 msg_blk->phy_odt_impedance);
940 debug("msg_blk->phy_drv_impedance = 0x%x\n",
941 msg_blk->phy_drv_impedance);
942 debug("msg_blk->bpznres_val = 0x%x\n", msg_blk->bpznres_val);
943 debug("msg_blk->enabled_dqs = 0x%x\n", msg_blk->enabled_dqs);
944 debug("msg_blk->acsm_odt_ctrl0 = 0x%x\n", msg_blk->acsm_odt_ctrl0);
945 debug("msg_blk->acsm_odt_ctrl1 = 0x%x\n", msg_blk->acsm_odt_ctrl1);
946 debug("msg_blk->acsm_odt_ctrl2 = 0x%x\n", msg_blk->acsm_odt_ctrl2);
947 debug("msg_blk->acsm_odt_ctrl3 = 0x%x\n", msg_blk->acsm_odt_ctrl3);
952 msg_blk_r = (struct ddr4r1d *)msg_blk;
992 msg_blk_lr = (struct ddr4lr1d *)msg_blk;
1002 memcpy(msg_blk_2d, msg_blk, sizeof(struct ddr4u1d));
1016 msg_blk->phy_cfg = (((msg_blk->mr3 & U(0x8)) != 0U) ||
1106 const struct ddr4lr1d *msg_blk;
1126 msg_blk = msg;
1132 if ((msg_blk->msg_misc & U(0x40)) != 0U) {