Lines Matching defs:input
21 #include "input.h"
609 const struct input *input, const void *msg)
618 if (input->basic.dimm_type != RDIMM) {
625 f0rc5x = (input->adv.phy_gen2_umctl_f0rc5x & U(0xff)) | U(0x500);
642 const struct input *input)
644 if (input->basic.dimm_type != RDIMM) {
656 const struct input *input)
663 cal_interval = input->adv.cal_interval;
664 cal_once = input->adv.cal_once;
673 const struct input *input)
682 frq = input->basic.frequency >> 1;
684 if (input->basic.frequency < 400) {
685 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3;
686 } else if (input->basic.frequency < 533) {
687 lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11;
733 const struct input *input,
749 load_pieimage(phy, input->basic.dimm_type);
751 prog_seq0bdly0(phy, input);
765 input->basic.dimm_type == RDIMM &&
766 input->adv.phy_gen2_umctl_opt == 1U ?
770 prog_acsm_playback(phy, input, msg); /* rdimm */
771 prog_acsm_ctr(phy, input); /* rdimm */
774 prog_cal_rate_run(phy, input);
777 input->basic.dimm_type == RDIMM ? U(0x2) : 0U);
783 static void phy_gen2_init_input(struct input *input)
787 input->adv.dram_byte_swap = 0;
788 input->adv.ext_cal_res_val = 0;
789 input->adv.tx_slew_rise_dq = 0xf;
790 input->adv.tx_slew_fall_dq = 0xf;
791 input->adv.tx_slew_rise_ac = 0xf;
792 input->adv.tx_slew_fall_ac = 0xf;
793 input->adv.mem_alert_en = 0;
794 input->adv.mem_alert_puimp = 5;
795 input->adv.mem_alert_vref_level = 0x29;
796 input->adv.mem_alert_sync_bypass = 0;
797 input->adv.cal_interval = 0x9;
798 input->adv.cal_once = 0;
799 input->adv.dis_dyn_adr_tri = 0;
800 input->adv.is2ttiming = 0;
801 input->adv.d4rx_preamble_length = 0;
802 input->adv.d4tx_preamble_length = 0;
805 debug("mr[%d] = 0x%x\n", i, input->mr[i]);
808 debug("input->cs_d0 = 0x%x\n", input->cs_d0);
809 debug("input->cs_d1 = 0x%x\n", input->cs_d1);
810 debug("input->mirror = 0x%x\n", input->mirror);
811 debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance);
812 debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance);
813 debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance);
816 debug("odt[%d] = 0x%x\n", i, input->odt[i]);
819 if (input->basic.dimm_type == RDIMM) {
821 debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]);
823 debug("input->rcw3x = 0x%x\n", input->rcw3x);
835 const struct input *input)
842 switch (input->basic.dimm_type) {
869 if (input->basic.dimm_type == LRDIMM) {
882 msg_blk->phy_vref = input->vref ? input->vref : U(0x61);
883 msg_blk->cs_present = input->cs_d0 | input->cs_d1;
884 msg_blk->cs_present_d0 = input->cs_d0;
885 msg_blk->cs_present_d1 = input->cs_d1;
886 if (input->mirror != 0) {
891 msg_blk->acsm_odt_ctrl0 = input->odt[0];
892 msg_blk->acsm_odt_ctrl1 = input->odt[1];
893 msg_blk->acsm_odt_ctrl2 = input->odt[2];
894 msg_blk->acsm_odt_ctrl3 = input->odt[3];
895 msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 +
896 input->basic.num_active_dbyte_dfi1) * 8;
897 msg_blk->x16present = input->basic.dram_data_width == 0x10 ?
909 msg_blk->mr0 = input->mr[0];
910 msg_blk->mr1 = input->mr[1];
911 msg_blk->mr2 = input->mr[2];
912 msg_blk->mr3 = input->mr[3];
913 msg_blk->mr4 = input->mr[4];
914 msg_blk->mr5 = input->mr[5];
915 msg_blk->mr6 = input->mr[6];
923 msg_blk->dramfreq = input->basic.frequency * 2U;
924 msg_blk->pll_bypass_en = input->basic.pll_bypass;
925 msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U :
926 input->basic.dfi_freq_ratio == 1U ? 2U :
928 msg_blk->bpznres_val = input->adv.ext_cal_res_val;
950 if (input->basic.dimm_type == RDIMM ||
951 input->basic.dimm_type == LRDIMM) {
954 msg_blk_r->f0rc00_d0 = input->rcw[0];
955 msg_blk_r->f0rc01_d0 = input->rcw[1];
956 msg_blk_r->f0rc02_d0 = input->rcw[2];
957 msg_blk_r->f0rc03_d0 = input->rcw[3];
958 msg_blk_r->f0rc04_d0 = input->rcw[4];
959 msg_blk_r->f0rc05_d0 = input->rcw[5];
960 msg_blk_r->f0rc06_d0 = input->rcw[6];
961 msg_blk_r->f0rc07_d0 = input->rcw[7];
962 msg_blk_r->f0rc08_d0 = input->rcw[8];
963 msg_blk_r->f0rc09_d0 = input->rcw[9];
964 msg_blk_r->f0rc0a_d0 = input->rcw[10];
965 msg_blk_r->f0rc0b_d0 = input->rcw[11];
966 msg_blk_r->f0rc0c_d0 = input->rcw[12];
967 msg_blk_r->f0rc0d_d0 = input->rcw[13];
968 msg_blk_r->f0rc0e_d0 = input->rcw[14];
969 msg_blk_r->f0rc0f_d0 = input->rcw[15];
970 msg_blk_r->f0rc3x_d0 = input->rcw3x;
973 msg_blk_r->f0rc00_d1 = input->rcw[0];
974 msg_blk_r->f0rc01_d1 = input->rcw[1];
975 msg_blk_r->f0rc02_d1 = input->rcw[2];
976 msg_blk_r->f0rc03_d1 = input->rcw[3];
977 msg_blk_r->f0rc04_d1 = input->rcw[4];
978 msg_blk_r->f0rc05_d1 = input->rcw[5];
979 msg_blk_r->f0rc06_d1 = input->rcw[6];
980 msg_blk_r->f0rc07_d1 = input->rcw[7];
981 msg_blk_r->f0rc08_d1 = input->rcw[8];
982 msg_blk_r->f0rc09_d1 = input->rcw[9];
983 msg_blk_r->f0rc0a_d1 = input->rcw[10];
984 msg_blk_r->f0rc0b_d1 = input->rcw[11];
985 msg_blk_r->f0rc0c_d1 = input->rcw[12];
986 msg_blk_r->f0rc0d_d1 = input->rcw[13];
987 msg_blk_r->f0rc0e_d1 = input->rcw[14];
988 msg_blk_r->f0rc0f_d1 = input->rcw[15];
989 msg_blk_r->f0rc3x_d1 = input->rcw3x;
991 if (input->basic.dimm_type == LRDIMM) {
1001 if (input->basic.train2d != 0) {
1018 : input->adv.is2ttiming;
1024 const struct input *input)
1033 tx_pre_p = input->adv.tx_slew_rise_dq;
1034 tx_pre_n = input->adv.tx_slew_fall_dq;
1039 for (byte = 0; byte < input->basic.num_dbyte; byte++) {
1051 const struct input *input)
1058 atx_pre_n = input->adv.tx_slew_fall_ac;
1059 atx_pre_p = input->adv.tx_slew_rise_ac;
1061 if (input->basic.num_anib == 8) {
1064 } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 ||
1065 input->basic.num_anib == 13) {
1069 ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib);
1073 for (anib = 0; anib < input->basic.num_anib; anib++) {
1089 const struct input *input)
1093 if (input->basic.dimm_type != RDIMM &&
1094 input->basic.dimm_type != LRDIMM) {
1098 phy_io_write16(phy, addr, input->adv.cast_cs_to_cid);
1103 const struct input *input,
1128 switch (input->basic.dimm_type) {
1172 const struct input *input)
1196 const struct input *input)
1201 if (input->basic.frequency / 2 < 235) {
1203 } else if (input->basic.frequency / 2 < 313) {
1205 } else if (input->basic.frequency / 2 < 469) {
1207 } else if (input->basic.frequency / 2 < 625) {
1209 } else if (input->basic.frequency / 2 < 938) {
1211 } else if (input->basic.frequency / 2 < 1067) {
1222 static void prog_dll_lck_param(uint16_t *phy, const struct input *input)
1230 static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input)
1239 const struct input *input)
1250 const struct input *input)
1255 if (input->basic.frequency >= 933) {
1265 const struct input *input)
1275 int two_tck_tx_dqs_pre = input->adv.d4tx_preamble_length;
1276 int two_tck_rx_dqs_pre = input->adv.d4rx_preamble_length;
1293 const struct input *input)
1298 if (input->adv.wdqsext != 0) {
1300 } else if (input->basic.frequency <= 933) {
1302 } else if (input->basic.frequency <= 1200) {
1303 if (input->adv.d4rx_preamble_length == 1) {
1309 if (input->adv.d4rx_preamble_length == 1) {
1383 const struct input *input)
1390 odtstren_p = map_odtstren_p(input->adv.odtimpedance,
1391 input->basic.hard_macro_ver);
1398 for (byte = 0; byte < input->basic.num_dbyte; byte++) {
1458 const struct input *input)
1465 drv_stren_fsdq_p = map_drvstren_fsdq_p(input->adv.tx_impedance,
1466 input->basic.hard_macro_ver);
1467 drv_stren_fsdq_n = map_drvstren_fsdq_n(input->adv.tx_impedance,
1468 input->basic.hard_macro_ver);
1472 for (byte = 0; byte < input->basic.num_dbyte; byte++) {
1556 const struct input *input)
1564 if (input->basic.hard_macro_ver == 4 &&
1565 input->adv.atx_impedance == 20) {
1570 adrv_stren_p = map_adrv_stren_p(input->adv.atx_impedance,
1571 input->basic.hard_macro_ver);
1572 adrv_stren_n = map_adrv_stren_n(input->adv.atx_impedance,
1573 input->basic.hard_macro_ver);
1576 for (anib = 0; anib < input->basic.num_anib; anib++) {
1584 const struct input *input)
1589 if (input->basic.dfi1exists == 1) {
1598 static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input)
1608 const struct input *input)
1617 const struct input *input)
1624 cal_drv_str_pu50 = input->adv.ext_cal_res_val;
1633 const struct input *input)
1638 cal_uclk_ticks_per1u_s = input->basic.frequency >> 1;
1648 const struct input *input)
1655 cal_interval = input->adv.cal_interval;
1656 cal_once = input->adv.cal_once;
1664 const struct input *input,
1686 const struct input *input)
1706 for (byte = 0; byte < input->basic.num_dbyte; byte++) {
1718 const struct input *input)
1730 if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) {
1733 malertpu_stren = input->adv.mem_alert_puimp;
1734 malertvref_level = input->adv.mem_alert_vref_level;
1735 malertsync_bypass = input->adv.mem_alert_sync_bypass;
1751 const struct input *input)
1756 dfi_freq_ratio = input->basic.dfi_freq_ratio;
1761 const struct input *input)
1769 dis_dyn_adr_tri = input->adv.dis_dyn_adr_tri;
1770 ddr2tmode = input->adv.is2ttiming;
1778 const struct input *input)
1786 pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */
1801 const struct input *input,
1816 for (byte = 0; byte < input->basic.num_dbyte; byte++) {
1818 if (byte <= input->basic.num_active_dbyte_dfi0 - 1) {
1820 if ((input->basic.dram_data_width != 4) &&
1837 const struct input *input)
1843 x4tg = input->basic.dram_data_width == 4 ? 0xf : 0;
1849 const struct input *input,
1860 const struct input *input)
1873 const struct input *input)
1895 const struct input *input,
1909 prog_dfi_phyupd(phy, input);
1910 prog_cal_misc2(phy, input);
1911 prog_tx_pre_drv_mode(phy, input);
1912 prog_atx_pre_drv_mode(phy, input);
1913 prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */
1914 prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg);
1915 prog_pll_ctrl2(phy, input);
1920 prog_pll_pwr_dn(phy, input);
1926 prog_ard_ptr_init_val(phy, input);
1927 prog_dqs_preamble_control(phy, input);
1928 prog_dll_lck_param(phy, input);
1929 prog_dll_gain_ctl(phy, input);
1930 prog_proc_odt_time_ctl(phy, input);
1931 prog_tx_odt_drv_stren(phy, input);
1932 prog_tx_impedance_ctrl1(phy, input);
1933 prog_atx_impedance(phy, input);
1934 prog_dfi_mode(phy, input);
1935 prog_dfi_camode(phy, input);
1936 prog_cal_drv_str0(phy, input);
1937 prog_cal_uclk_info(phy, input);
1938 prog_cal_rate(phy, input);
1939 prog_vref_in_global(phy, input, msg);
1940 prog_dq_dqs_rcv_cntrl(phy, input);
1941 prog_mem_alert_control(phy, input);
1942 prog_dfi_freq_ratio(phy, input);
1943 prog_tristate_mode_ca(phy, input);
1944 prog_dfi_xlat(phy, input);
1945 prog_dbyte_misc_mode(phy, input, msg);
1946 prog_master_x4config(phy, input);
1947 prog_dmipin_present(phy, input, msg);
1948 prog_acx4_anib_dis(phy, input);
2146 static int g_exec_fw(uint16_t **phy_ptr, int train2d, struct input *input)
2158 prog_pll_ctrl2(phy, input);
2159 prog_pll_ctrl(phy, input);
2203 struct input *input,
2218 switch (input->basic.dimm_type) {
2403 static void print_jason_format(struct input *input,
2409 printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]);
2410 printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]);
2411 printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver);
2412 printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte);
2413 printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte_dfi0);
2414 printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib);
2415 printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0);
2416 printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates);
2417 printf("\n \"frequency\": \"%d\",", input->basic.frequency);
2418 printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
2419 printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
2420 printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists);
2421 printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width);
2422 printf("\n \"dram_byte_swap\": \"0x%04x\",", (unsigned int)input->adv.dram_byte_swap);
2423 printf("\n \"ext_cal_res_val\": \"0x%04x\",", (unsigned int)input->adv.ext_cal_res_val);
2424 printf("\n \"tx_slew_rise_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_dq);
2425 printf("\n \"tx_slew_fall_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_dq);
2426 printf("\n \"tx_slew_rise_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_ac);
2427 printf("\n \"tx_slew_fall_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_ac);
2428 printf("\n \"odt_impedance\": \"%d\",", input->adv.odtimpedance);
2429 printf("\n \"tx_impedance\": \"%d\",", input->adv.tx_impedance);
2430 printf("\n \"atx_impedance\": \"%d\",", input->adv.atx_impedance);
2431 printf("\n \"mem_alert_en\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_en);
2432 printf("\n \"mem_alert_pu_imp\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_puimp);
2433 printf("\n \"mem_alert_vref_level\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_vref_level);
2434 printf("\n \"mem_alert_sync_bypass\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_sync_bypass);
2435 printf("\n \"cal_interval\": \"0x%04x\",", (unsigned int)input->adv.cal_interval);
2436 printf("\n \"cal_once\": \"0x%04x\",", (unsigned int)input->adv.cal_once);
2437 printf("\n \"dis_dyn_adr_tri\": \"0x%04x\",", (unsigned int)input->adv.dis_dyn_adr_tri);
2438 printf("\n \"is2t_timing\": \"0x%04x\",", (unsigned int)input->adv.is2ttiming);
2439 printf("\n \"d4rx_preabmle_length\": \"0x%04x\",", (unsigned int)input->adv.d4rx_preamble_length);
2440 printf("\n \"d4tx_preamble_length\": \"0x%04x\",", (unsigned int)input->adv.d4tx_preamble_length);
2490 static struct input input;
2508 zeromem(&input, sizeof(input));
2512 input.basic.dram_type = DDR4;
2514 input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM;
2515 input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 +
2517 input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte;
2518 input.basic.num_rank_dfi0 = dimm_param->n_ranks;
2519 input.basic.dram_data_width = dimm_param->device_width;
2520 input.basic.hard_macro_ver = 0xa;
2521 input.basic.num_pstates = 1;
2522 input.basic.dfi_freq_ratio = 1;
2523 input.basic.num_anib = 0xc;
2524 input.basic.train2d = popts->skip2d ? 0 : 1;
2525 input.basic.frequency = (int) (clk / 2000000ul);
2526 debug("frequency = %dMHz\n", input.basic.frequency);
2527 input.cs_d0 = conf->cs_on_dimm[0];
2529 input.cs_d1 = conf->cs_on_dimm[1];
2531 input.mirror = dimm_param->mirrored_dimm;
2532 input.mr[0] = regs->sdram_mode[0] & U(0xffff);
2533 input.mr[1] = regs->sdram_mode[0] >> 16U;
2534 input.mr[2] = regs->sdram_mode[1] >> 16U;
2535 input.mr[3] = regs->sdram_mode[1] & U(0xffff);
2536 input.mr[4] = regs->sdram_mode[8] >> 16U;
2537 input.mr[5] = regs->sdram_mode[8] & U(0xffff);
2538 input.mr[6] = regs->sdram_mode[9] >> 16U;
2539 input.vref = popts->vref_phy;
2540 debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U);
2547 parse_odt(odt_rd, true, i, input.cs_d0, input.cs_d1,
2548 input.odt);
2549 parse_odt(odt_wr, false, i, input.cs_d0, input.cs_d1,
2550 input.odt);
2557 input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf);
2558 input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf);
2559 input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf);
2560 input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf);
2561 input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf);
2562 input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf);
2563 input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf);
2564 input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf);
2565 input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf);
2566 input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf);
2567 input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf);
2568 input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf);
2569 input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf);
2570 input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf);
2571 input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf);
2572 input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf);
2573 input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff);
2576 input.adv.odtimpedance = popts->odt ? popts->odt : 60;
2577 input.adv.tx_impedance = popts->phy_tx_impedance ?
2579 input.adv.atx_impedance = popts->phy_atx_impedance ?
2582 debug("Initializing input adv data structure\n");
2583 phy_gen2_init_input(&input);
2586 ret = phy_gen2_msg_init(&msg_1d, &msg_2d, &input);
2592 ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d);
2605 input.basic.train2d
2631 ret = load_fw(priv->phy, &input, 0, &msg_1d,
2640 ret = g_exec_fw(priv->phy, 0, &input);
2651 get_cdd_val(priv->phy, rank, input.basic.frequency,
2658 if ((ret == 0) && (input.basic.train2d != 0)) {
2661 ret = load_fw(priv->phy, &input, 1, &msg_2d,
2670 ret = g_exec_fw(priv->phy, 1, &input);
2689 input.basic.train2d
2704 i_load_pie(priv->phy, &input, &msg_1d);
2707 input.basic.dimm_type == RDIMM ? "RDIMM" :
2708 input.basic.dimm_type == LRDIMM ? "LRDIMM" :
2715 print_jason_format(&input, &msg_1d, &msg_2d);