Lines Matching defs:addr
37 static uint32_t map_phy_addr_space(uint32_t addr)
40 uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */
41 uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */
42 uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */
43 uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */
70 static inline uint16_t *phy_io_addr(void *phy, uint32_t addr)
72 return phy + (map_phy_addr_space(addr) << 2);
75 static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data)
77 mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data);
79 printf("0x%06x,0x%x\n", addr, data);
83 static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr)
85 uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr));
88 printf("R: 0x%06x,0x%x\n", addr, reg);
99 static void read_phy_reg(uint16_t *phy, uint32_t addr,
105 buf[i] = phy_io_read16(phy, (addr + i));
415 value = phy_io_read16(phy, training_1D_values[i].addr);
418 training_1D_values[i].addr, value,
420 training_1D_values[i].addr));
433 training_2D_values[i].addr);
436 debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n",
437 i, training_2D_values[i].addr,
439 training_2D_values[i].addr));
516 phy_io_write16(phy, training_1D_values[i].addr,
520 training_1D_values[i].addr,
523 training_1D_values[i].addr));
545 phy_io_write16(phy, training_2D_values[i].addr,
549 training_2D_values[i].addr,
552 training_1D_values[i].addr));
604 phy_io_write16(phy, image[i].addr, image[i].data);
661 uint32_t addr;
668 addr = t_master | csr_cal_rate_addr;
669 phy_io_write16(phy, addr, cal_rate);
677 uint32_t addr;
710 addr = t_master | csr_seq0bdly0_addr;
711 phy_io_write16(phy, addr, ps_count[0]);
713 debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr));
715 addr = t_master | csr_seq0bdly1_addr;
716 phy_io_write16(phy, addr, ps_count[1]);
718 debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr));
720 addr = t_master | csr_seq0bdly2_addr;
721 phy_io_write16(phy, addr, ps_count[2]);
723 debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr));
725 addr = t_master | csr_seq0bdly3_addr;
726 phy_io_write16(phy, addr, ps_count[3]);
728 debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr));
1029 uint32_t addr;
1043 addr = p_addr | t_dbyte | c_addr | b_addr |
1045 phy_io_write16(phy, addr, tx_slew_rate);
1056 uint32_t addr;
1083 addr = t_anib | c_addr | csr_atx_slew_rate_addr;
1084 phy_io_write16(phy, addr, atx_slew_rate);
1091 uint32_t addr = t_master | csr_enable_cs_multicast_addr;
1098 phy_io_write16(phy, addr, input->adv.cast_cs_to_cid);
1174 uint32_t addr;
1179 addr = t_master | csr_pll_ctrl1_addr;
1180 phy_io_write16(phy, addr, pll_ctrl1);
1182 debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr));
1184 addr = t_master | csr_pll_test_mode_addr;
1185 phy_io_write16(phy, addr, pll_test_mode);
1187 debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr));
1189 addr = t_master | csr_pll_ctrl4_addr;
1190 phy_io_write16(phy, addr, pll_ctrl4);
1192 debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr));
1199 uint32_t addr = t_master | csr_pll_ctrl2_addr;
1217 phy_io_write16(phy, addr, pll_ctrl2);
1219 debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr));
1224 uint32_t addr = t_master | csr_dll_lockparam_addr;
1226 phy_io_write16(phy, addr, U(0x212));
1227 debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr));
1232 uint32_t addr = t_master | csr_dll_gain_ctl_addr;
1234 phy_io_write16(phy, addr, U(0x61));
1235 debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr));
1241 uint32_t addr;
1243 addr = t_master | csr_pll_pwr_dn_addr;
1244 phy_io_write16(phy, addr, 0U);
1246 debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr));
1253 uint32_t addr = t_master | csr_ard_ptr_init_val_addr;
1261 phy_io_write16(phy, addr, ard_ptr_init_val);
1268 uint32_t addr = t_master | csr_dqs_preamble_control_addr;
1285 phy_io_write16(phy, addr, data);
1288 addr = t_master | csr_dbyte_dll_mode_cntrl_addr;
1289 phy_io_write16(phy, addr, data);
1296 uint32_t addr = t_master | csr_proc_odt_time_ctl_addr;
1315 phy_io_write16(phy, addr, proc_odt_time_ctl);
1388 uint32_t addr;
1402 addr = t_dbyte | c_addr | b_addr |
1404 phy_io_write16(phy, addr, tx_odt_drv_stren);
1463 uint32_t addr;
1476 addr = t_dbyte | c_addr | b_addr |
1478 phy_io_write16(phy, addr, tx_impedance_ctrl1);
1562 uint32_t addr;
1578 addr = t_anib | c_addr | csr_atx_impedance_addr;
1579 phy_io_write16(phy, addr, atx_impedance);
1587 uint32_t addr;
1594 addr = t_master | csr_dfi_mode_addr;
1595 phy_io_write16(phy, addr, dfi_mode);
1600 uint32_t addr;
1602 addr = t_master | csr_acx4_anib_dis_addr;
1603 phy_io_write16(phy, addr, 0x0);
1604 debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr));
1611 uint32_t addr = t_master | csr_dfi_camode_addr;
1613 phy_io_write16(phy, addr, dfi_camode);
1622 uint32_t addr;
1628 addr = t_master | csr_cal_drv_str0_addr;
1629 phy_io_write16(phy, addr, cal_drv_str0);
1636 uint32_t addr;
1643 addr = t_master | csr_cal_uclk_info_addr;
1644 phy_io_write16(phy, addr, cal_uclk_ticks_per1u_s);
1653 uint32_t addr;
1659 addr = t_master | csr_cal_rate_addr;
1660 phy_io_write16(phy, addr, cal_rate);
1670 uint32_t addr;
1681 addr = t_master | csr_vref_in_global_addr;
1682 phy_io_write16(phy, addr, vref_in_global);
1695 uint32_t addr;
1710 addr = t_dbyte | c_addr | b_addr |
1712 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl);
1728 uint32_t addr;
1743 addr = t_master | csr_mem_alert_control_addr;
1744 phy_io_write16(phy, addr, mem_alert_control);
1745 addr = t_master | csr_mem_alert_control2_addr;
1746 phy_io_write16(phy, addr, mem_alert_control2);
1754 uint32_t addr = t_master | csr_dfi_freq_ratio_addr;
1757 phy_io_write16(phy, addr, dfi_freq_ratio);
1767 uint32_t addr = t_master | csr_tristate_mode_ca_addr;
1774 phy_io_write16(phy, addr, tristate_mode_ca);
1783 uint32_t addr;
1795 addr = t_master | (csr_dfi_freq_xlat0_addr + loop_vector);
1796 phy_io_write16(phy, addr, dfifreqxlat_dat);
1808 uint32_t addr;
1822 addr = t_dbyte
1825 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1_1);
1828 addr = t_dbyte | c_addr | csr_dbyte_misc_mode_addr;
1829 phy_io_write16(phy, addr, dbyte_misc_mode);
1830 addr = t_dbyte | c_addr | csr_dq_dqs_rcv_cntrl1_addr;
1831 phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1);
1841 uint32_t addr = t_master | csr_master_x4config_addr;
1845 phy_io_write16(phy, addr, master_x4config);
1853 uint32_t addr = t_master | csr_dmipin_present_addr;
1856 phy_io_write16(phy, addr, dmipin_present);
1863 uint32_t addr;
1865 addr = t_master | (csr_dfiphyupd_addr);
1866 dfiphyupd_dat = phy_io_read16(phy, addr) &
1869 phy_io_write16(phy, addr, dfiphyupd_dat);
1876 uint32_t addr;
1878 addr = t_master | (csr_cal_misc2_addr);
1879 cal_misc2_dat = phy_io_read16(phy, addr) |
1882 phy_io_write16(phy, addr, cal_misc2_dat);
1884 addr = t_master | (csr_cal_offsets_addr);
1887 cal_offsets_dat = (phy_io_read16(phy, addr) & ~csr_cal_drv_pdth_mask)
1890 phy_io_write16(phy, addr, cal_offsets_dat);