Lines Matching defs:regs
31 struct ddr_cfg_regs *regs,
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) |
70 debug(" _config = 0x%x\n", regs->cs[i].config);
90 struct ddr_cfg_regs *regs,
228 regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) |
236 debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]);
253 regs->timing_cfg[1] = (((pretoact_mclk & 0x0F) << 28) |
261 debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]);
270 regs->timing_cfg[2] = (((additive_latency & 0xf) << 28) |
278 debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]);
280 regs->timing_cfg[3] = (((ext_pretoact & 0x1) << 28) |
288 debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]);
290 regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) |
299 debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]);
306 regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) |
310 debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]);
312 regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) |
317 debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]);
320 par_lat = (regs->sdram_rcw[1] & 0xf) + 1;
324 regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) |
329 debug("timing_cfg[7] = 0x%x\n", regs->timing_cfg[7]);
341 regs->timing_cfg[8] = (((rwt_bg & 0xf) << 28) |
348 debug("timing_cfg[8] = 0x%x\n", regs->timing_cfg[8]);
350 regs->timing_cfg[9] = (refrec_cid_mclk & 0x3ff) << 16 |
352 debug("timing_cfg[9] = 0x%x\n", regs->timing_cfg[9]);
356 struct ddr_cfg_regs *regs,
377 rc0f = (regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) ? rc0f : 4;
378 regs->sdram_rcw[0] =
387 regs->sdram_rcw[1] =
396 regs->sdram_rcw[2] =
399 debug("sdram_rcw[0] = 0x%x\n", regs->sdram_rcw[0]);
400 debug("sdram_rcw[1] = 0x%x\n", regs->sdram_rcw[1]);
401 debug("sdram_rcw[2] = 0x%x\n", regs->sdram_rcw[2]);
405 struct ddr_cfg_regs *regs,
450 regs->sdram_cfg[0] = ((mem_en & 0x1) << 31) |
468 debug("sdram_cfg[0] = 0x%x\n", regs->sdram_cfg[0]);
478 regs->sdram_cfg[1] = (0
493 debug("sdram_cfg[1] = 0x%x\n", regs->sdram_cfg[1]);
495 regs->sdram_cfg[2] = (rd_pre & 0x1) << 16 |
501 regs->sdram_cfg[2] |= ((pdimm->package_3ds + 1) >> 1)
505 debug("sdram_cfg[2] = 0x%x\n", regs->sdram_cfg[2]);
510 struct ddr_cfg_regs *regs,
517 regs->interval = ((refint & 0xFFFF) << 16) |
519 debug("interval = 0x%x\n", regs->interval);
524 struct ddr_cfg_regs *regs,
633 regs->sdram_mode[0] = (((esdmode & 0xFFFF) << 16) |
635 debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]);
673 regs->sdram_mode[1] = ((esdmode2 & 0xFFFF) << 16) |
675 debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]);
684 regs->sdram_mode[9] = ((esdmode6 & 0xffff) << 16) |
686 debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]);
736 ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) {
741 if (((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) &&
756 regs->sdram_mode[8] = ((esdmode4 & 0xffff) << 16) |
758 debug("sdram_mode[8] = 0x%x\n", regs->sdram_mode[8]);
761 regs->sdram_mode[2] = (((esdmode & 0xFFFF) << 16) |
763 regs->sdram_mode[3] = ((esdmode2 & 0xFFFF) << 16) |
765 regs->sdram_mode[10] = ((esdmode4 & 0xFFFF) << 16) |
767 regs->sdram_mode[11] = ((esdmode6 & 0xFFFF) << 16) |
769 debug("sdram_mode[2] = 0x%x\n", regs->sdram_mode[2]);
770 debug("sdram_mode[3] = 0x%x\n", regs->sdram_mode[3]);
771 debug("sdram_mode[10] = 0x%x\n", regs->sdram_mode[10]);
772 debug("sdram_mode[11] = 0x%x\n", regs->sdram_mode[11]);
775 regs->sdram_mode[4] = (((esdmode & 0xFFFF) << 16) |
777 regs->sdram_mode[5] = ((esdmode2 & 0xFFFF) << 16) |
779 regs->sdram_mode[12] = ((esdmode4 & 0xFFFF) << 16) |
781 regs->sdram_mode[13] = ((esdmode6 & 0xFFFF) << 16) |
783 debug("sdram_mode[4] = 0x%x\n", regs->sdram_mode[4]);
784 debug("sdram_mode[5] = 0x%x\n", regs->sdram_mode[5]);
785 debug("sdram_mode[12] = 0x%x\n", regs->sdram_mode[12]);
786 debug("sdram_mode[13] = 0x%x\n", regs->sdram_mode[13]);
789 regs->sdram_mode[6] = (((esdmode & 0xFFFF) << 16) |
791 regs->sdram_mode[7] = ((esdmode2 & 0xFFFF) << 16) |
793 regs->sdram_mode[14] = ((esdmode4 & 0xFFFF) << 16) |
795 regs->sdram_mode[15] = ((esdmode6 & 0xFFFF) << 16) |
797 debug("sdram_mode[6] = 0x%x\n", regs->sdram_mode[6]);
798 debug("sdram_mode[7] = 0x%x\n", regs->sdram_mode[7]);
799 debug("sdram_mode[14] = 0x%x\n", regs->sdram_mode[14]);
800 debug("sdram_mode[15] = 0x%x\n", regs->sdram_mode[15]);
811 static void cal_ddr_data_init(struct ddr_cfg_regs *regs)
813 regs->data_init = CONFIG_MEM_INIT_VALUE;
816 static void cal_ddr_dq_mapping(struct ddr_cfg_regs *regs,
819 const unsigned int acc_ecc_en = (regs->sdram_cfg[0] >> 2) & 0x1;
821 regs->dq_map[0] = ((pdimm->dq_mapping[0] & 0x3F) << 26) |
827 regs->dq_map[1] = ((pdimm->dq_mapping[5] & 0x3F) << 26) |
833 regs->dq_map[2] = ((pdimm->dq_mapping[12] & 0x3F) << 26) |
840 regs->dq_map[3] = ((pdimm->dq_mapping[17] & 0x3F) << 26) |
845 debug("dq_map[0] = 0x%x\n", regs->dq_map[0]);
846 debug("dq_map[1] = 0x%x\n", regs->dq_map[1]);
847 debug("dq_map[2] = 0x%x\n", regs->dq_map[2]);
848 debug("dq_map[3] = 0x%x\n", regs->dq_map[3]);
850 static void cal_ddr_zq_cntl(struct ddr_cfg_regs *regs)
858 regs->zq_cntl = ((zq_en & 0x1) << 31) |
863 debug("zq_cntl = 0x%x\n", regs->zq_cntl);
866 static void cal_ddr_sr_cntr(struct ddr_cfg_regs *regs,
872 regs->ddr_sr_cntr = (sr_it & 0xF) << 16;
873 debug("ddr_sr_cntr = 0x%x\n", regs->ddr_sr_cntr);
876 static void cal_ddr_eor(struct ddr_cfg_regs *regs,
880 regs->eor = 0x40000000; /* address hash enable */
881 debug("eor = 0x%x\n", regs->eor);
885 static void cal_ddr_csn_bnds(struct ddr_cfg_regs *regs,
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) |
905 cal_csn_config(i, regs, popts, pdimm);
908 regs->cs[i].bnds = 0xffffffff;
911 debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds);
915 static void cal_ddr_addr_dec(struct ddr_cfg_regs *regs)
920 const unsigned int cs0_config = regs->cs[0].config;
950 ba_intlv = (regs->sdram_cfg[0] >> 8) & 0x7f;
971 dbw = (regs->sdram_cfg[0] >> 19) & 0x3;
1101 regs->dec[0] = map_row[17] << 26 |
1105 regs->dec[1] = map_row[13] << 26 |
1109 regs->dec[2] = map_row[9] << 26 |
1113 regs->dec[3] = map_row[5] << 26 |
1117 regs->dec[4] = map_row[1] << 26 |
1121 regs->dec[5] = map_col[8] << 26 |
1125 regs->dec[6] = map_col[4] << 26 |
1129 regs->dec[7] = map_col[0] << 26 |
1133 regs->dec[8] = map_cid[1] << 26 |
1137 regs->dec[9] = map_bg[0] << 26 |
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]);
1325 struct ddr_cfg_regs *regs,
1335 zeromem(regs, sizeof(struct ddr_cfg_regs));
1374 cal_ddr_csn_bnds(regs, popts, conf, pdimm);
1375 cal_ddr_sdram_cfg(clk, regs, popts, pdimm, ip_rev);
1376 cal_ddr_sdram_rcw(clk, regs, popts, pdimm);
1377 cal_timing_cfg(clk, regs, popts, pdimm, conf, cas_latency,
1379 cal_ddr_dq_mapping(regs, pdimm);
1382 cal_ddr_addr_dec(regs);
1385 cal_ddr_sdram_mode(clk, regs, popts, conf, pdimm, cas_latency,
1387 cal_ddr_eor(regs, popts);
1388 cal_ddr_data_init(regs);
1389 cal_ddr_sdram_interval(clk, regs, popts, pdimm);
1390 cal_ddr_zq_cntl(regs);
1391 cal_ddr_sr_cntr(regs, popts);