Lines Matching defs:regs
189 const struct ddr_cfg_regs *regs,
196 const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
214 ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]);
216 ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl);
221 (regs->cs[i].bnds & U(0xfffefffe)) >> 1U);
223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
225 ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2);
228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]);
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]);
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]);
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]);
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]);
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]);
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]);
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]);
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]);
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]);
238 ddr_out32(&ddr->zq_cntl, regs->zq_cntl);
240 ddr_out32(&ddr->dq_map[i], regs->dq_map[i]);
242 ddr_out32(&ddr->sdram_cfg_3, regs->sdram_cfg[2]);
243 ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]);
244 ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]);
245 ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]);
246 ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]);
247 ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]);
248 ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]);
249 ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]);
250 ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]);
251 ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]);
252 ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]);
253 ddr_out32(&ddr->sdram_mode_11, regs->sdram_mode[10]);
254 ddr_out32(&ddr->sdram_mode_12, regs->sdram_mode[11]);
255 ddr_out32(&ddr->sdram_mode_13, regs->sdram_mode[12]);
256 ddr_out32(&ddr->sdram_mode_14, regs->sdram_mode[13]);
257 ddr_out32(&ddr->sdram_mode_15, regs->sdram_mode[14]);
258 ddr_out32(&ddr->sdram_mode_16, regs->sdram_mode[15]);
259 ddr_out32(&ddr->sdram_md_cntl, regs->md_cntl);
262 regs->interval & ~SDRAM_INTERVAL_BSTOPRE);
264 ddr_out32(&ddr->sdram_interval, regs->interval);
266 ddr_out32(&ddr->sdram_data_init, regs->data_init);
267 if (regs->eor != 0) {
268 ddr_out32(&ddr->eor, regs->eor);
271 ddr_out32(&ddr->wrlvl_cntl, regs->wrlvl_cntl[0]);
278 if (regs->wrlvl_cntl[1] != 0) {
279 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->wrlvl_cntl[1]);
281 if (regs->wrlvl_cntl[2] != 0) {
282 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->wrlvl_cntl[2]);
286 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
287 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->sdram_rcw[0]);
288 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->sdram_rcw[1]);
289 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->sdram_rcw[2]);
290 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->sdram_rcw[3]);
291 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->sdram_rcw[4]);
292 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->sdram_rcw[5]);
293 ddr_out32(&ddr->ddr_cdr2, regs->cdr[1]);
294 ddr_out32(&ddr->sdram_cfg_2, regs->sdram_cfg[1]);
295 ddr_out32(&ddr->init_addr, regs->init_addr);
296 ddr_out32(&ddr->init_ext_addr, regs->init_ext_addr);
300 if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
301 if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
303 regs->sdram_rcw[1] & ~0xf0);
307 regs->err_disable | DDR_ERR_DISABLE_APED);
310 ddr_out32(&ddr->err_disable, regs->err_disable);
312 ddr_out32(&ddr->err_int_en, regs->err_int_en);
321 if (regs->tx_cfg[i] != 0) {
322 ddr_out32(&ddr->tx_cfg[i], regs->tx_cfg[i]);
326 if (regs->debug[i] != 0) {
332 ddr_out32(&ddr->debug[i], regs->debug[i]);
336 if ((regs->dec[9] & 1) != 0U) {
338 ddr_out32(&ddr->dec[i], regs->dec[i]);
355 regs->cdr[1] | DDR_CDR2_VREF_TRAIN_EN);
368 if (regs->debug[28] != 0) {
370 tmp |= regs->debug[28] & 0xff;
405 (regs->cs[i].config & ~CTLR_INTLV_MASK));
407 ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config);
413 temp_sdram_cfg = regs->sdram_cfg[0];
456 if ((regs->cs[i].config & 0x80000000) == 0) {
460 ((regs->cs[i].config >> 14) & 0x3) + 2 +
461 ((regs->cs[i].config >> 8) & 0x7) + 12 +
462 ((regs->cs[i].config >> 4) & 0x3) + 0 +
463 ((regs->cs[i].config >> 0) & 0x7) + 8 +
464 ((regs->sdram_cfg[2] >> 4) & 0x3) +
465 3 - ((regs->sdram_cfg[0] >> 19) & 0x3) -
503 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
505 ddr_out32(&ddr->csn_cfg[0], regs->cs[0].config);
507 if ((regs->dec[9] & U(0x1)) != 0U) {
509 ddr_out32(&ddr->dec[9], regs->dec[9]);
516 if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
522 if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
524 if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0) {
537 regs->err_disable & ~DDR_ERR_DISABLE_APED);
542 ddr_out32(&ddr->sdram_interval, regs->interval);
550 tmp = (regs->sdram_cfg[0] >> 19) & 0x3;
560 if ((regs->sdram_cfg[0] & SDRAM_CFG_ECC_EN) != 0) {