Lines Matching defs:ddr
15 #include <ddr.h>
39 int bist(const struct ccsr_ddr *ddr, int timeout)
59 uint32_t dec_9 = ddr_in32(&ddr->dec[9]);
66 cs0_config = ddr_in32(&ddr->csn_cfg[0]);
70 csn_bnds[i] = ddr_in32(&ddr->bnds[i].a);
71 ddr_out32(&ddr->bnds[i].a,
74 ddr_out32(&ddr->csn_cfg[0], cs0_config & ~CTLR_INTLV_MASK);
81 temp32 = ddr_in32(&ddr->dec[i >> 2U]);
92 map_save = ddr_in32(&ddr->dec[pos >> 2]);
98 ddr_out32(&ddr->dec[pos >> 2U], temp32);
105 ddr_out32(&ddr->mtp[i], test_pattern[i]);
108 ddr_out32(&ddr->mtcr, mtcr);
111 mtcr = ddr_in32(&ddr->mtcr);
119 err_detect = ddr_in32(&ddr->err_detect);
120 err_sbe = ddr_in32(&ddr->err_sbe);
128 ddr_out32(&ddr->bnds[i].a, csn_bnds[i]);
130 ddr_out32(&ddr->csn_cfg[0], cs0_config);
133 ddr_out32(&ddr->dec[pos >> 2], map_save);
147 void dump_ddrc(unsigned int *ddr)
153 for (i = 0U; i < U(0x400); i++, ddr++) {
154 val = ddr_in32(ddr);
156 debug("*0x%lx = 0x%lx\n", (unsigned long)ddr, val);
190 const struct ccsr_ddr *ddr,
214 ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]);
216 ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl);
220 ddr_out32(&ddr->bnds[i].a,
223 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
225 ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2);
228 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]);
229 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]);
230 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]);
231 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]);
232 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]);
233 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]);
234 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]);
235 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]);
236 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]);
237 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]);
238 ddr_out32(&ddr->zq_cntl, regs->zq_cntl);
240 ddr_out32(&ddr->dq_map[i], regs->dq_map[i]);
242 ddr_out32(&ddr->sdram_cfg_3, regs->sdram_cfg[2]);
243 ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]);
244 ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]);
245 ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]);
246 ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]);
247 ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]);
248 ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]);
249 ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]);
250 ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]);
251 ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]);
252 ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]);
253 ddr_out32(&ddr->sdram_mode_11, regs->sdram_mode[10]);
254 ddr_out32(&ddr->sdram_mode_12, regs->sdram_mode[11]);
255 ddr_out32(&ddr->sdram_mode_13, regs->sdram_mode[12]);
256 ddr_out32(&ddr->sdram_mode_14, regs->sdram_mode[13]);
257 ddr_out32(&ddr->sdram_mode_15, regs->sdram_mode[14]);
258 ddr_out32(&ddr->sdram_mode_16, regs->sdram_mode[15]);
259 ddr_out32(&ddr->sdram_md_cntl, regs->md_cntl);
261 ddr_out32(&ddr->sdram_interval,
264 ddr_out32(&ddr->sdram_interval, regs->interval);
266 ddr_out32(&ddr->sdram_data_init, regs->data_init);
268 ddr_out32(&ddr->eor, regs->eor);
271 ddr_out32(&ddr->wrlvl_cntl, regs->wrlvl_cntl[0]);
279 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->wrlvl_cntl[1]);
282 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->wrlvl_cntl[2]);
286 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
287 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->sdram_rcw[0]);
288 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->sdram_rcw[1]);
289 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->sdram_rcw[2]);
290 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->sdram_rcw[3]);
291 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->sdram_rcw[4]);
292 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->sdram_rcw[5]);
293 ddr_out32(&ddr->ddr_cdr2, regs->cdr[1]);
294 ddr_out32(&ddr->sdram_cfg_2, regs->sdram_cfg[1]);
295 ddr_out32(&ddr->init_addr, regs->init_addr);
296 ddr_out32(&ddr->init_ext_addr, regs->init_ext_addr);
302 ddr_out32(&ddr->ddr_sdram_rcw_2,
306 ddr_out32(&ddr->err_disable,
310 ddr_out32(&ddr->err_disable, regs->err_disable);
312 ddr_out32(&ddr->err_int_en, regs->err_int_en);
315 if (get_ddrc_version(ddr) == 0x50500) {
316 ddr_out32(&ddr->tx_cfg[1], 0x1f1f1f1f);
317 ddr_out32(&ddr->debug[3], 0x124a02c0);
322 ddr_out32(&ddr->tx_cfg[i], regs->tx_cfg[i]);
332 ddr_out32(&ddr->debug[i], regs->debug[i]);
338 ddr_out32(&ddr->dec[i], regs->dec[i]);
342 ddr_out32(&ddr->dec[9], 0);
350 if (get_ddrc_version(ddr) == 0x50200) {
352 } else if (get_ddrc_version(ddr) == 0x50201) {
353 ddr_out32(&ddr->debug[37], (U(1) << 31));
354 ddr_out32(&ddr->ddr_cdr2,
363 tmp = ddr_in32(&ddr->debug[28]);
374 ddr_out32(&ddr->debug[28], tmp);
380 tmp = ddr_in32(&ddr->debug[28]);
381 ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
404 ddr_out32(&ddr->csn_cfg[i],
407 ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config);
415 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
417 if (get_ddrc_version(ddr) < U(0x50500)) {
431 while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) != 0) &&
438 ddr_in32(&ddr->ddr_dsr2));
445 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg);
448 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
476 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
481 if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) {
488 ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0);
491 if (ddr_in32(&ddr->debug[1]) & 0x3d00) {
493 ddr_in32(&ddr->debug[1]));
503 ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
505 ddr_out32(&ddr->csn_cfg[0], regs->cs[0].config);
509 ddr_out32(&ddr->dec[9], regs->dec[9]);
520 } while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
527 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
536 ddr_out32(&ddr->err_disable,
542 ddr_out32(&ddr->sdram_interval, regs->interval);
549 } while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
553 tmp = ddr_in32(&ddr->debug[9 + i]);
561 tmp = ddr_in32(&ddr->debug[13]);
567 tmp = ddr_in32(&ddr->debug[28]);
578 if ((ddr_in32(&ddr->debug[1]) &
579 ((get_ddrc_version(ddr) == 0x50500) ? 0x3c00 : 0x3d00)) != 0) {
581 ddr_in32(&ddr->debug[1]));
589 ret = bist(ddr, timeout);
591 dump_ddrc((void *)ddr);