Lines Matching defs:ret

87 	int ret;
89 	ret = spi_nor_read_sr(&sr);
90 	if (ret != 0) {
91 		return ret;
97 		ret = spi_nor_read_fsr(&fsr);
98 		if (ret != 0) {
99 			return ret;
111 	int ret;
115 		ret = spi_nor_ready();
116 		if (ret <= 0) {
117 			return ret;
127 	int ret;
129 	ret = spi_nor_read_sr(&sr);
130 	if (ret != 0) {
131 		return ret;
138 	ret = spi_nor_write_en();
139 	if (ret != 0) {
140 		return ret;
144 	ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
145 	if (ret != 0) {
146 		return ret;
149 	ret = spi_nor_wait_ready();
150 	if (ret != 0) {
151 		return ret;
154 	ret = spi_nor_read_sr(&sr);
155 	if ((ret != 0) || ((sr & SR_QUAD_EN_MX) == 0U)) {
164 	int ret;
166 	ret = spi_nor_write_en();
167 	if (ret != 0) {
168 		return ret;
171 	ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
172 	if (ret != 0) {
176 	ret = spi_nor_wait_ready();
177 	if (ret != 0) {
178 		return ret;
187 	int ret;
189 	ret = spi_nor_read_cr(&sr_cr[1]);
190 	if (ret != 0) {
191 		return ret;
199 	ret = spi_nor_read_sr(&sr_cr[0]);
200 	if (ret != 0) {
201 		return ret;
204 	ret = spi_nor_write_sr_cr(sr_cr);
205 	if (ret != 0) {
206 		return ret;
209 	ret = spi_nor_read_cr(&sr_cr[1]);
210 	if ((ret != 0) || ((sr_cr[1] & CR_QUAD_EN_SPAN) == 0U)) {
219 	int ret;
227 	ret = spi_nor_write_en();
228 	if (ret != 0) {
229 		return ret;
239 	int ret;
245 	ret = spi_nor_write_en();
246 	if (ret != 0) {
247 		return ret;
250 	ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
252 	if (ret != 0) {
253 		return ret;
264 	int ret;
266 	ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
268 	if (ret != 0) {
269 		return ret;
281 	int ret;
291 			ret = spi_nor_write_bar(nor_dev.read_op.addr.val);
292 			if (ret != 0) {
293 				return ret;
303 		ret = spi_mem_exec_op(&nor_dev.read_op);
304 		if (ret != 0) {
306 			return ret;
316 		ret = spi_nor_clean_bar();
317 		if (ret != 0) {
318 			return ret;
327 	int ret;
350 	ret = spi_nor_read_id(&id);
351 	if (ret != 0) {
352 		return ret;
372 			ret = spi_nor_macronix_quad_enable();
377 			ret = spi_nor_quad_enable();
382 	if ((ret == 0) && ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U)) {
383 		ret = spi_nor_read_bar();
386 	return ret;