Lines Matching defs:mci_index
22 #define MCI_WRITE_READ_DATA_REG(mci_index) \
23 MVEBU_MCI_REG_BASE_REMAP(mci_index)
27 #define MCI_ACCESS_CMD_REG(mci_index) \
28 (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4)
292 static int mci_poll_command_completion(int mci_index, int command_type)
305 mci_cmd_value = mci_mmio_read_32(MCI_ACCESS_CMD_REG(mci_index));
343 static int mci_axi_set_pcie_mode(int mci_index)
353 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
358 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
366 if (mci_poll_command_completion(mci_index, MCI_CMD_WRITE) == 0) {
368 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
375 if (mci_poll_command_completion(mci_index, MCI_CMD_READ) == 0) {
377 MCI_WRITE_READ_DATA_REG(mci_index));
388 static int mci_axi_set_fifo_thresh(int mci_index)
406 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data);
407 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
410 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
413 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
416 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
420 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
427 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data);
428 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
431 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
438 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data);
439 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
442 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
445 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
447 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
451 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
457 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data);
458 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
462 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
475 static int mci_axi_set_fifo_rx_tx_thresh(int mci_index)
481 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
483 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
487 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
490 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
492 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
496 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
499 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
502 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
506 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
509 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
511 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
515 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
518 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
520 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
524 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
527 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
529 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
533 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
536 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
540 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
545 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
548 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
552 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
557 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
568 static int mci_enable_simultaneous_transactions(int mci_index)
574 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
578 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
582 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
585 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
588 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
593 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
596 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index),
599 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
604 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
610 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff);
611 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
616 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
622 mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), 0xffffffff);
623 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
628 ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE);
647 static _Bool mci_simulatenous_trans_missing(int mci_index)
656 mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index),
662 ret = mci_poll_command_completion(mci_index, MCI_CMD_READ);
664 reg = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index));
690 int mci_configure(int mci_index)
699 if (mci_simulatenous_trans_missing(mci_index)) {
701 mci_index);
705 rval = mci_enable_simultaneous_transactions(mci_index);
712 rval = mci_axi_set_pcie_mode(mci_index);
717 rval = mci_axi_set_fifo_thresh(mci_index);
722 rval = mci_axi_set_fifo_rx_tx_thresh(mci_index);
823 int mci_link_tune(int mci_index)
828 INFO("MCI%d initialization:\n", mci_index);
830 ret = mci_configure(mci_index);