Lines Matching defs:mask
116 uint32_t reg, mask, field;
120 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
122 field = reg & mask;
125 reg &= ~mask;
135 uint32_t reg, mask, field;
139 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
141 field = reg & mask;
149 reg &= ~mask;
159 uint32_t reg, mask;
174 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset;
176 reg &= ~mask;
256 uint32_t mask = COMMON_SELECTOR_COMPHY_MASK << shift;
265 reg &= ~mask;
305 uint32_t mask, data;
316 mask = data;
317 data = polling_with_timeout(addr, data, mask,
335 uint32_t mask, data;
338 data = mask = 0x0U;
341 mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK;
347 mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK;
351 reg_set(addr, data, mask);
358 uint32_t mask, data;
385 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
387 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
389 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
391 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
393 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
401 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
403 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
405 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
417 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
420 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
422 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
433 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
436 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
439 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
442 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
445 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
447 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
449 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
451 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
453 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
455 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK;
457 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK;
459 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
462 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
465 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
468 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
471 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
474 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK;
476 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
479 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
482 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
485 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK;
488 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK;
491 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK;
493 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK;
495 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
497 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
500 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK;
502 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK;
504 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
506 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK;
508 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK;
510 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK;
512 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK;
514 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
517 mask = HPIPE_SMAPLER_MASK;
519 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
520 mask = HPIPE_SMAPLER_MASK;
522 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
525 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
527 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
530 mask = HPIPE_DFE_RES_FORCE_MASK;
532 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
535 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
537 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
539 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
542 mask = HPIPE_G3_FFE_CAP_SEL_MASK;
545 mask |= HPIPE_G3_FFE_RES_SEL_MASK;
548 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK;
550 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
552 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
554 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
557 mask = HPIPE_G3_DFE_RES_MASK;
559 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
562 mask = HPIPE_OS_PH_OFFSET_MASK;
564 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK;
566 mask |= HPIPE_OS_PH_VALID_MASK;
568 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
569 mask = HPIPE_OS_PH_VALID_MASK;
571 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
572 mask = HPIPE_OS_PH_VALID_MASK;
574 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
577 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
579 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
582 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
585 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
588 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
591 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
594 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
597 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
600 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK;
602 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK;
605 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK;
608 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK;
611 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
614 mask = HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK;
617 mask |= HPIPE_G2_SET_2_G2_TX_EMPH0_MASK;
620 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
623 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK;
625 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK;
628 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK;
631 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK;
634 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK;
636 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK;
638 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
641 mask = HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK;
644 mask |= HPIPE_G3_SET_2_G3_TX_EMPH0_MASK;
647 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask);
650 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK;
652 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
683 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode);
701 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
703 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
705 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
708 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
710 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
711 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
727 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
729 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
731 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
733 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
736 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
738 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
740 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
745 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
747 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
749 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
757 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK;
759 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
764 mask = HPIPE_MISC_REFCLK_SEL_MASK;
766 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
768 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
770 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
772 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
774 mask = HPIPE_LOOPBACK_SEL_MASK;
776 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
778 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
780 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
782 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
784 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
786 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
797 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
799 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
801 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
803 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
810 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
812 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
817 mask = data;
818 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
826 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
828 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
830 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
843 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
894 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
896 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
898 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
903 mask = COMMON_PHY_CFG6_IF_40_SEL_MASK;
905 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
908 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
910 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
912 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
914 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
916 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
918 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
920 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
923 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
925 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
927 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
929 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
931 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
933 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
935 mask |= SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
937 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
946 mask = SD_EXTERNAL_CONFIG1_TX_IDLE_MASK;
948 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
953 mask = HPIPE_MISC_ICP_FORCE_MASK;
957 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
959 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
961 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
963 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
965 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
967 mask = HPIPE_LOOPBACK_SEL_MASK;
969 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
971 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
973 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
975 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
977 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
979 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
983 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK;
985 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK;
987 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK;
989 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK;
992 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK;
995 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
1000 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
1002 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
1004 mask = HPIPE_DFE_RES_FORCE_MASK;
1006 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1009 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1012 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
1015 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1019 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK;
1022 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK;
1026 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1028 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
1031 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
1034 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1036 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
1038 mask |= HPIPE_TX_REG1_SLC_EN_MASK;
1040 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1042 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
1044 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
1046 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1048 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
1050 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1053 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1056 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1058 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1061 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1064 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1067 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
1070 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
1073 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK;
1076 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1079 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1081 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1083 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1086 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1088 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1090 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
1094 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
1096 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1098 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
1100 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1102 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
1105 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
1108 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
1110 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1113 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
1117 data, mask);
1120 mask = HPIPE_CAL_OS_PH_EXT_MASK;
1124 data, mask);
1127 mask = HPIPE_DFE_RES_FORCE_MASK;
1129 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1132 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1135 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1139 mask = HPIPE_RX_TRAIN_TIMER_MASK;
1141 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1144 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1146 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1149 mask = HPIPE_TX_PRESET_INDEX_MASK;
1151 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1154 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1156 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1159 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK;
1161 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK;
1163 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1166 mask = HPIPE_TRAIN_PAT_NUM_MASK;
1168 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1171 mask = HPIPE_DME_ETHERNET_MODE_MASK;
1173 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1176 mask = HPIPE_CAL_VDD_CONT_MODE_MASK;
1178 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1181 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK;
1183 mask |= HPIPE_SMAPLER_MASK;
1185 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1186 mask = HPIPE_SMAPLER_MASK;
1188 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1191 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1193 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1197 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1199 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1201 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1203 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1209 mask = data;
1210 data = polling_with_timeout(addr, data, mask,
1222 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1224 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1229 mask = data;
1230 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1238 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1240 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1242 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1261 uint32_t reg, mask, data, pcie_width;
1337 mask = COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK;
1339 data, mask);
1342 mask = COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK;
1343 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1354 mask = DFX_DEV_GEN_PCIE_CLK_SRC_MASK;
1356 DFX_DEV_GEN_CTRL12_REG, data, mask);
1361 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1363 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1365 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1367 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1369 mask |= COMMON_PHY_PHY_MODE_MASK;
1371 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1374 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1376 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1378 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1385 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
1388 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
1391 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
1394 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
1396 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
1399 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
1402 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
1404 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
1406 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
1410 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
1412 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
1413 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
1414 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
1422 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
1425 mask = HPIPE_CFG_UPDATE_POLARITY_MASK;
1426 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask);
1429 mask = HPIPE_DFE_CTRL_28_PIPE4_MASK;
1430 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask);
1433 mask = 0;
1437 mask |= HPIPE_MISC_CLK100M_125M_MASK;
1441 mask |= HPIPE_MISC_TXDCLK_2X_MASK;
1444 mask |= HPIPE_MISC_CLK500_EN_MASK;
1448 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1452 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
1455 mask |= HPIPE_MISC_ICP_FORCE_MASK;
1457 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1460 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1464 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1468 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1470 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1474 mask = HPIPE_LANE_ALIGN_OFF_MASK;
1476 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
1488 mask = HPIPE_INTERFACE_GEN_MAX_MASK;
1491 mask |= HPIPE_INTERFACE_DET_BYPASS_MASK;
1494 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
1496 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
1499 mask = HPIPE_PCIE_IDLE_SYNC_MASK;
1502 mask |= HPIPE_PCIE_SEL_BITS_MASK;
1504 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
1507 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
1510 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
1513 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
1515 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1518 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
1521 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
1523 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1527 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
1529 mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
1531 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
1533 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
1536 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
1538 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
1540 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
1542 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
1544 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1547 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
1549 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1552 mask = HPIPE_TRX_TRAIN_TIMER_MASK;
1554 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
1557 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
1560 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1563 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
1565 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1568 mask = HPIPE_G3_DFE_RES_MASK;
1570 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
1573 mask = HPIPE_DFE_RES_FORCE_MASK;
1575 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1578 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK;
1581 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK;
1584 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK;
1586 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
1589 mask = HPIPE_SMAPLER_MASK;
1591 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1593 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
1596 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
1598 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
1600 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
1603 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK;
1605 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1608 mask = HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK;
1610 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK;
1612 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK;
1614 mask |= HPIPE_CDR_MAX_DFE_ADAPT_1_MASK;
1616 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
1618 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK;
1620 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
1623 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
1625 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
1627 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
1629 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
1632 mask = HPIPE_G2_DFE_RES_MASK;
1634 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
1637 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK;
1639 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
1642 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK;
1644 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1647 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK;
1649 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
1652 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK;
1654 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK;
1656 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK;
1658 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
1660 mask = HPIPE_CFG_EQ_BUNDLE_DIS_MASK;
1662 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask);
1676 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK;
1678 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK;
1679 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1711 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK;
1721 mask = COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK;
1724 data, mask);
1734 mask = data;
1735 data = polling_with_timeout(addr, data, mask,
1754 uint32_t mask, data;
1770 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1772 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1774 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1788 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1790 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1792 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1794 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1796 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1798 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1800 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
1802 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1805 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1807 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1809 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1811 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1813 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1815 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1817 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1829 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1831 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1833 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1838 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1840 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1842 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1862 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1864 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
1866 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1868 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1870 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1872 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1874 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1877 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1879 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1883 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1885 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1887 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1889 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1896 mask = data;
1897 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
1915 mask = data;
1916 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1926 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1928 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1941 uint32_t mask, data;
1964 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1966 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1968 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1970 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1972 mask |= COMMON_PHY_PHY_MODE_MASK;
1974 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1977 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
1979 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
1981 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1989 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
1992 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
1995 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
1998 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
2000 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
2010 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
2013 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
2015 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
2047 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
2050 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
2053 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
2055 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
2057 mask = HPIPE_G2_TX_SSC_AMP_MASK;
2059 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
2073 mask = data;
2074 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
2090 uint32_t mask, data;
2097 mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK;
2099 mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK;
2101 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
2104 mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
2106 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK;
2108 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
2110 mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK;
2112 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2114 mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK;
2116 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
2118 mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK;
2120 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
2122 mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK;
2124 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
2126 mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK;
2128 mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
2130 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2136 uint32_t mask, data, timeout;
2154 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
2156 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2159 mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
2162 data, mask);
2165 mask = HPIPE_DFE_RES_FORCE_MASK;
2167 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2171 mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
2173 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2177 mask = HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET |
2182 if (data & mask)
2201 mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
2203 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2207 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK;
2210 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET);
2212 mask = HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK;
2215 & mask) >> HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET);
2217 mask = HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK;
2219 & mask) >> HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET);
2221 mask = HPIPE_ADAPTED_DFE_RES_MASK;
2224 & mask) >> HPIPE_ADAPTED_DFE_RES_OFFSET);
2241 mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
2243 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2246 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2253 mask = HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
2255 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2258 mask = HPIPE_DFE_RES_FORCE_MASK;
2260 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2263 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
2265 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
2303 uint32_t mask, data;
2313 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
2315 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
2317 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
2343 uint32_t mask, data;
2354 mask = SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
2357 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2433 uint32_t mask, data;
2481 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
2483 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
2485 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
2487 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2515 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
2517 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
2519 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask);