Lines Matching defs:hpipe_addr
357 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr;
375 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
382 hpipe_addr, sd_ip_addr, comphy_addr);
413 reg_set(hpipe_addr + HPIPE_MISC_REG,
422 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
424 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
428 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
447 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
459 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
476 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
497 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
514 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
519 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
522 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
527 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
532 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
539 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
554 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
559 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
568 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
571 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
574 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
588 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
597 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
611 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
620 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
638 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
647 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask);
655 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
658 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
663 mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
667 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
670 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
682 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
688 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
766 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
772 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
776 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
782 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
786 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
791 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
842 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
882 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
959 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
965 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
969 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
975 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
979 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
995 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
1006 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1026 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1034 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1040 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1046 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1050 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1076 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1083 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1088 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1100 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1110 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1115 reg_set(hpipe_addr +
1122 reg_set(hpipe_addr +
1129 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1135 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1141 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1146 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1151 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1156 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1163 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1168 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1173 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1178 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1185 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1188 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1193 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1263 uintptr_t hpipe_addr, comphy_addr, addr;
1282 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1396 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
1406 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
1422 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
1426 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask);
1430 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask);
1457 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1470 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1476 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
1483 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
1496 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
1504 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
1515 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1523 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1533 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
1544 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1549 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1554 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
1560 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1565 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1570 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
1575 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1586 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
1591 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1593 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
1600 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
1605 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1616 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
1620 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
1629 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
1634 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
1639 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
1644 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1649 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
1658 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
1662 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask);
1699 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
1753 uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
1759 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
1825 reg_set(hpipe_addr + HPIPE_MISC_REG,
1833 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1835 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1842 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1844 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
1855 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
1858 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1868 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1874 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1879 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1940 uintptr_t hpipe_addr, comphy_addr, addr;
1958 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2000 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
2002 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
2006 reg_set(hpipe_addr + HPIPE_MISC_REG,
2015 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
2017 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
2021 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
2025 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
2029 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
2033 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
2041 mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
2055 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
2059 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
2064 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
2071 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
2077 hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
2089 uintptr_t hpipe_addr;
2092 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2101 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
2108 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
2112 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2116 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
2120 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
2124 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
2130 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2138 uintptr_t hpipe_addr;
2144 hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
2156 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2161 reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
2167 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2173 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2181 data = mmio_read_32(hpipe_addr + HPIPE_INTERRUPT_1_REGISTER);
2189 hpipe_addr + HPIPE_INTERRUPT_1_REGISTER, data);
2203 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2208 g1_ffe_res_sel = ((mmio_read_32(hpipe_addr +
2213 g1_ffe_cap_sel = ((mmio_read_32(hpipe_addr +
2218 align90 = ((mmio_read_32(hpipe_addr + HPIPE_DATA_PHASE_OFF_CTRL_REG)
2222 g1_dfe_res = ((mmio_read_32(hpipe_addr +
2231 (hpipe_addr + HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG),
2232 mmio_read_32(hpipe_addr +
2234 (hpipe_addr + HPIPE_DATA_PHASE_OFF_CTRL_REG),
2235 mmio_read_32(hpipe_addr + HPIPE_DATA_PHASE_OFF_CTRL_REG),
2236 (hpipe_addr + HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG),
2237 mmio_read_32(hpipe_addr + HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG));
2243 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2255 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2260 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2265 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);