Lines Matching defs:data
305 uint32_t mask, data;
314 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
316 mask = data;
317 data = polling_with_timeout(addr, data, mask,
319 if (data != 0) {
320 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)
322 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)
335 uint32_t mask, data;
338 data = mask = 0x0U;
340 data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET);
346 data |= (1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET);
351 reg_set(addr, data, mask);
358 uint32_t mask, data;
386 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
388 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
390 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
392 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
393 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
395 /* Set select data width 40Bit - SATA mode only */
402 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
404 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
405 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
418 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
421 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
422 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
427 /* Set select data width 40Bit (SEL_BITS[2:0]) */
434 data = sata_static_values->g1_rx_selmupi <<
437 data |= sata_static_values->g1_rx_selmupf <<
440 data |= sata_static_values->g1_rx_selmufi <<
443 data |= sata_static_values->g1_rx_selmuff <<
446 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
447 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
450 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
452 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
454 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
456 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET;
458 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET;
459 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
463 data = sata_static_values->g2_rx_selmupi <<
466 data |= sata_static_values->g2_rx_selmupf <<
469 data |= sata_static_values->g2_rx_selmufi <<
472 data |= sata_static_values->g2_rx_selmuff <<
475 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET;
476 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
480 data = sata_static_values->g3_rx_selmupi <<
483 data |= sata_static_values->g3_rx_selmupf <<
486 data |= sata_static_values->g3_rx_selmufi <<
489 data |= sata_static_values->g3_rx_selmuff <<
492 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET;
494 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET;
496 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
497 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
501 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET;
503 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET;
505 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
507 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET;
509 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET;
511 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET;
513 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET;
514 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
518 data = 0x1 << HPIPE_SMAPLER_OFFSET;
519 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
521 data = 0x0 << HPIPE_SMAPLER_OFFSET;
522 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
526 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
527 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
531 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
532 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
536 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
538 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
539 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
543 data = sata_static_values->g3_ffe_cap_sel <<
546 data |= sata_static_values->g3_ffe_res_sel <<
549 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET;
551 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
553 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
554 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
558 data = sata_static_values->g3_dfe_res << HPIPE_G3_DFE_RES_OFFSET;
559 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
563 data = sata_static_values->align90 << HPIPE_OS_PH_OFFSET_OFFSET;
565 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET;
567 data |= 0x0 << HPIPE_OS_PH_VALID_OFFSET;
568 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
570 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET;
571 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
573 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET;
574 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask);
578 data = sata_static_values->g1_amp << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
580 data |= sata_static_values->g1_tx_amp_adj <<
583 data |= sata_static_values->g1_emph <<
586 data |= sata_static_values->g1_emph_en <<
588 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
592 data = sata_static_values->g1_tx_emph_en <<
595 data |= sata_static_values->g1_tx_emph <<
597 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
601 data = sata_static_values->g2_amp << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET;
603 data |= sata_static_values->g2_tx_amp_adj <<
606 data |= sata_static_values->g2_emph <<
609 data |= sata_static_values->g2_emph_en <<
611 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask);
615 data = sata_static_values->g2_tx_emph_en <<
618 data |= sata_static_values->g2_tx_emph <<
620 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
624 data = sata_static_values->g3_amp << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET;
626 data |= sata_static_values->g3_tx_amp_adj <<
629 data |= sata_static_values->g3_emph <<
632 data |= sata_static_values->g3_emph_en <<
635 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET;
637 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET;
638 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask);
642 data = sata_static_values->g3_tx_emph_en <<
645 data |= sata_static_values->g3_tx_emph <<
647 reg_set(hpipe_addr + HPIPE_G3_SET_2_REG, data, mask);
651 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET;
652 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
683 uint32_t mask, data, sgmii_speed = COMPHY_GET_SPEED(comphy_mode);
702 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
704 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
705 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
709 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
715 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
716 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
719 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
720 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
728 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
730 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
732 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
733 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
737 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
739 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
741 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
742 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
746 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
748 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
749 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
754 /* Make sure that 40 data bits is disabled
758 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET;
759 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
765 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
766 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
769 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
771 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
772 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
775 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
776 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
779 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
781 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
782 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
785 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
786 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
788 /* Set analog parameters from ETP(HW) - for now use the default data */
798 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
800 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
802 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
803 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
811 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
812 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
816 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
817 mask = data;
818 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
819 if (data != 0) {
827 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
829 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
830 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
843 uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
895 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
897 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
898 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
900 /* Make sure that 40 data bits is disabled
904 data = 0 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET;
905 reg_set(comphy_addr + COMMON_PHY_CFG6_REG, data, mask);
909 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
911 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
913 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
915 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
917 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
919 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
920 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
924 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
926 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
928 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
929 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
932 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
934 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
936 data |= 0x1 << SD_EXTERNAL_CONFIG1_TX_IDLE_OFFSET;
937 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
947 data = 0x0U;
948 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
954 data = (speed == COMPHY_SPEED_5_15625G) ?
958 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
959 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
962 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
964 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
965 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
968 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
969 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
972 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
974 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
975 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
978 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
979 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
984 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET;
986 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET;
988 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET;
990 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET;
993 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET;
995 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);
1001 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
1002 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
1005 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
1006 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1010 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1013 data = xfi_static_values->g1_amp <<
1016 data |= xfi_static_values->g1_emph <<
1020 data |= xfi_static_values->g1_emph_en <<
1023 data |= xfi_static_values->g1_tx_amp_adj <<
1026 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1029 data = xfi_static_values->g1_tx_emph <<
1032 data |= xfi_static_values->g1_tx_emph_en <<
1034 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1037 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
1039 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
1040 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1043 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1045 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
1046 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1049 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1050 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1054 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1057 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1059 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
1062 data |= xfi_static_values->g1_rx_selmupi <<
1065 data |= xfi_static_values->g1_rx_selmupf <<
1068 data |= xfi_static_values->g1_rx_selmufi <<
1071 data |= xfi_static_values->g1_rx_selmuff <<
1074 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET;
1076 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1080 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1082 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1083 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1087 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1088 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1091 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
1095 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
1097 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
1099 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
1100 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1103 data |= xfi_static_values->g1_ffe_cap_sel <<
1106 data |= xfi_static_values->g1_ffe_res_sel <<
1109 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
1110 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1114 data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
1117 data, mask);
1121 data = xfi_static_values->align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
1124 data, mask);
1128 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
1129 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1133 data = xfi_static_values->g1_dfe_res <<
1135 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1140 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET;
1141 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1145 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1146 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1150 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET;
1151 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask);
1155 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1156 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1160 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET;
1162 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET;
1163 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1167 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET;
1168 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask);
1172 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET;
1173 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask);
1177 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET;
1178 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask);
1182 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET;
1184 data |= 0x1 << HPIPE_SMAPLER_OFFSET;
1185 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1187 data = 0x0 << HPIPE_SMAPLER_OFFSET;
1188 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1192 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1193 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1198 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1200 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1202 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1203 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1207 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1209 mask = data;
1210 data = polling_with_timeout(addr, data, mask,
1212 if (data != 0) {
1213 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)
1215 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)
1223 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1224 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1228 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1229 mask = data;
1230 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1231 if (data != 0) {
1239 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1241 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1242 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1245 data = mmio_read_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index));
1246 data |= COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
1247 mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
1249 data &= ~COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
1250 mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
1261 uint32_t reg, mask, data, pcie_width;
1336 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET;
1339 data, mask);
1341 data = 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET;
1343 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1352 data = DFX_DEV_GEN_PCIE_CLK_SRC_MUX <<
1356 DFX_DEV_GEN_CTRL12_REG, data, mask);
1362 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1364 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1366 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1368 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1370 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
1371 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1375 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1377 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1378 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1386 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
1389 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
1392 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
1395 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
1396 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
1398 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
1401 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
1403 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
1406 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
1409 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
1416 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
1417 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
1419 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
1422 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
1424 data = 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET;
1426 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, data, mask);
1428 data = 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET;
1430 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, data, mask);
1434 data = 0;
1438 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
1442 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
1445 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
1449 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1453 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
1456 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
1457 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
1461 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1465 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1469 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1470 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1475 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
1476 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
1489 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
1492 data |= 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET;
1495 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
1496 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
1500 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
1503 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
1504 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
1508 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
1511 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
1514 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
1515 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1519 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
1522 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
1523 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
1528 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
1530 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
1532 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
1533 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
1537 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
1539 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
1541 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
1543 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
1544 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
1548 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
1549 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
1553 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
1554 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
1559 data = 0;
1560 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
1564 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
1565 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
1569 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
1570 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
1574 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
1575 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1579 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;
1582 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;
1585 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET;
1586 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);
1590 data = 0x1 << HPIPE_SMAPLER_OFFSET;
1591 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
1597 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
1599 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
1600 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
1604 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET;
1605 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask);
1609 data = 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET;
1611 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET;
1613 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET;
1615 data |= 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET;
1616 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
1619 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET;
1620 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask);
1624 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
1626 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
1628 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
1629 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
1633 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET;
1634 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask);
1638 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET;
1639 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
1643 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET;
1644 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask);
1648 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET;
1649 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask);
1653 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET;
1655 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET;
1657 data |= 0x6 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET;
1658 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask);
1661 data = 0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET;
1662 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG2_REG, data, mask);
1674 data = 0x0;
1679 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, data, mask);
1707 data = (COMPHY_LANE0 <<
1713 data = (COMPHY_LANE0 <<
1724 data, mask);
1733 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
1734 mask = data;
1735 data = polling_with_timeout(addr, data, mask,
1738 if (data) {
1754 uint32_t mask, data;
1771 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1773 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1774 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1789 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1791 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1793 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1795 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1797 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1799 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1801 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
1802 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1806 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1808 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1810 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1811 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1814 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1816 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1817 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1830 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1832 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1833 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1839 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1841 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1842 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1863 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1865 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
1867 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1868 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1871 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1873 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1874 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1878 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1879 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1884 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1886 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1888 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1889 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1894 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1896 mask = data;
1897 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
1898 if (data != 0) {
1900 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1902 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1903 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1914 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1915 mask = data;
1916 data = polling_with_timeout(addr, data, mask, 100, REG_32BIT);
1917 if (data != 0) {
1919 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1927 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1929 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1930 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1941 uint32_t mask, data;
1965 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1967 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1969 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1971 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1973 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
1974 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1978 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
1980 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
1981 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1990 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
1993 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
1996 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
1999 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
2000 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
2011 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
2014 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
2015 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
2024 /* Set select data width 20Bit (SEL_BITS[2:0]) */
2048 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
2051 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
2054 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
2055 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
2058 data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET;
2059 reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
2072 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
2073 mask = data;
2074 data = polling_with_timeout(addr, data, mask, 15000, REG_32BIT);
2075 if (data != 0) {
2077 hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
2090 uint32_t mask, data;
2098 data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF);
2100 data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF);
2101 reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
2105 data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
2107 data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF);
2108 reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
2111 data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF);
2112 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2115 data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF);
2116 reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
2119 data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF);
2120 reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
2123 data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET);
2124 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
2127 data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF);
2129 data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
2130 reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
2136 uint32_t mask, data, timeout;
2155 data = 0 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
2156 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2160 data = 0 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
2162 data, mask);
2166 data = 0 << HPIPE_DFE_RES_FORCE_OFFSET;
2167 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2172 data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
2173 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2181 data = mmio_read_32(hpipe_addr + HPIPE_INTERRUPT_1_REGISTER);
2182 if (data & mask)
2189 hpipe_addr + HPIPE_INTERRUPT_1_REGISTER, data);
2191 if (timeout == 0 || data & HPIPE_TRX_TRAIN_TIME_OUT_INT_MASK) {
2196 if (data & HPIPE_TRX_TRAIN_FAILED_MASK) {
2202 data = 0x0 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
2203 reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
2242 data = g1_ffe_res_sel << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
2243 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2247 data = g1_ffe_cap_sel << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
2248 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2254 data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
2255 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
2259 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
2260 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
2264 data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
2265 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
2303 uint32_t mask, data;
2314 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
2316 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
2317 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
2343 uint32_t mask, data;
2355 data = ((command == COMPHY_COMMAND_DIGITAL_PWR_OFF) ?
2357 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2433 uint32_t mask, data;
2460 data = mmio_read_32(comphy_base +
2462 data >>= (COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index);
2463 data &= COMMON_SELECTOR_COMPHY_MASK;
2464 if (data == COMMON_SELECTOR_PIPE_COMPHY_PCIE)
2482 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
2484 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
2486 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
2487 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
2496 data = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) +
2500 data &= ~PCIE_MAC_RESET_MASK_PORT0;
2503 data &= ~PCIE_MAC_RESET_MASK_PORT1;
2506 data &= ~PCIE_MAC_RESET_MASK_PORT2;
2511 SYS_CTRL_UINIT_SOFT_RESET_REG, data);
2516 data = 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
2518 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
2519 reg_set(comphy_ip_addr + COMMON_PHY_CFG1_REG, data, mask);