Lines Matching defs:reg_base
614 uintptr_t reg_base = 0;
632 reg_base = COMPHY_INDIRECT_REG;
636 reg_base = USB3_GBE1_PHY;
649 usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask);
661 usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask);
666 usb3_reg_set(reg_base, COMPHY_LANE_CFG4,
673 usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL,
680 usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0,
688 usb3_reg_set(reg_base, COMPHY_GEN2_SET2,
697 usb3_reg_set(reg_base, COMPHY_GEN3_SET2,
719 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask);
724 usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask);
730 usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK);
736 usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK);
741 usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT,
747 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL,
762 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask);
767 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN, PHY_GEN_MAX_USB3_5G,
773 usb3_reg_set(reg_base, COMPHY_GEN2_SET3,
780 usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK);
787 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
790 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET;
794 ret = polling_with_timeout(LANE_STAT1_ADDR(USB3) + reg_base,