Lines Matching defs:offset

217 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
226 	 * offset is 0x200
229 		mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset);
232 			      offset + USB3PHY_LANE2_REG_BASE_OFFSET);
291 	uint32_t offset, data = 0, ref_clk;
304 	offset =  COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
305 	comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
313 	offset = COMPHY_SYNC_PATTERN + SATAPHY_LANE2_REG_BASE_OFFSET;
314 	comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
318 	offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET;
319 	comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
323 	offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
329 	comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
333 	offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
334 	comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
375 	uintptr_t offset;
407 	offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
408 	reg_set(offset, data, mask);
413 	reg_set(offset, data, mask);
434 	reg_set(offset, data, mask);
595 	uintptr_t offset;
602 	offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
603 	reg_set(offset, data, mask);
959 	uint32_t offset;
964 	offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
965 	comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
969 	offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
970 	comphy_sata_set_indirect(comphy_indir_regs, offset, 0,