Lines Matching defs:data
38 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
49 /* 40M1G25 mode init data */
217 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask);
240 uint16_t data, uint16_t mask)
242 comphy_set_indirect(addr, reg_offset, data, mask, true);
247 uint16_t data, uint16_t mask)
249 comphy_set_indirect(addr, reg_offset, data, mask, false);
254 uint16_t data, uint16_t mask)
256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask);
291 uint32_t offset, data = 0, ref_clk;
309 data |= TXD_INVERT_BIT;
311 data |= RXD_INVERT_BIT;
314 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
317 /* 1. Select 40-bit data width width */
374 uint32_t mask, data;
404 data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
405 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
408 reg_set(offset, data, mask);
411 data = 0;
413 reg_set(offset, data, mask);
421 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET;
422 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET;
425 data |= SD_SPEED_3_125_G << GEN_RX_SEL_OFFSET;
426 data |= SD_SPEED_3_125_G << GEN_TX_SEL_OFFSET;
434 reg_set(offset, data, mask);
443 data = PHY_MODE_SGMII;
445 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
451 data = 0;
453 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask);
460 data = REF_FREF_SEL_SERDES_50MHZ;
462 data = REF_FREF_SEL_SERDES_25MHZ;
465 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
475 * 11. Program COMPHY register SEL_BITS to set correct parallel data
478 data = DATA_WIDTH_10BIT;
481 data, mask);
521 data = 0x0;
523 data |= TXD_INVERT_BIT;
525 data |= RXD_INVERT_BIT;
527 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN, sd_ip_addr), data, mask);
560 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
596 uint32_t mask, data;
600 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
601 mask = data;
603 reg_set(offset, data, mask);
616 uint32_t mask, data, cfg, ref_clk;
617 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data,
660 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
661 usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask);
717 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
719 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask);
723 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
724 usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask);
729 data = IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN;
730 usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK);
735 data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN;
736 usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK);
739 * 11. Set 20-bit data width
754 data = 0U;
756 data |= TXD_INVERT_BIT;
759 data |= RXD_INVERT_BIT;
762 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask);
779 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
780 usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK);
786 data = COMPHY_LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET;
788 data);
813 uint32_t mask, data;
876 data = 0U;
878 data |= TXD_INVERT_BIT;
881 data |= RXD_INVERT_BIT;
884 reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
887 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
888 mask = data | SOFT_RESET | MODE_REFDIV_MASK;
889 reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
1020 uint32_t data, addr;
1030 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
1033 if (data != 0) {