Lines Matching defs:ap_index

70 static void dump_ccu(int ap_index)
80 		win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
84 			alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index,
86 			ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index,
94 	win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index));
117 int ccu_is_win_enabled(int ap_index, uint32_t win_id)
119 	return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) &
123 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id)
138 	mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr);
139 	mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr);
144 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg);
147 static void ccu_disable_win(int ap_index, uint32_t win_id)
156 	win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
158 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg);
169 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size)
176 		ccu_enable_win(ap_index, win, win_id);
185 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size)
195 		target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
199 		base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id));
207 		ccu_disable_win(ap_index, win_id);
218 static uint32_t ccu_dram_target_get(int ap_index)
225 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;
228 	target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
235 void ccu_dram_target_set(int ap_index, uint32_t target)
242 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;
245 	dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id));
248 	mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr);
252 void ccu_dram_win_config(int ap_index, struct addr_map_win *win)
259 	const uint32_t win_id = (ap_index == 0) ? 2 : 1;
269 	ccu_disable_win(ap_index, win_id);
271 	mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),
274 	ccu_enable_win(ap_index, win, win_id);
317 int init_ccu(int ap_index)
335 	marvell_get_ccu_memory_map(ap_index, &win, &win_count);
350 	dram_target = ccu_dram_target_get(ap_index);
352 	mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);
371 		ccu_disable_win(ap_index, win_id);
373 		mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id),
384 		ccu_enable_win(ap_index, win, win_id);
390 	win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK)
392 	mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg);
395 	dump_ccu(ap_index);