Lines Matching defs:ap_index
21 #define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200)
26 void llc_cache_sync(int ap_index)
28 mmio_write_32(LLC_SYNC(ap_index), 0);
32 void llc_flush_all(int ap_index)
34 mmio_write_32(LLC_CLEAN_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
35 llc_cache_sync(ap_index);
38 void llc_clean_all(int ap_index)
40 mmio_write_32(LLC_CLEAN_WAY(ap_index), LLC_ALL_WAYS_MASK);
41 llc_cache_sync(ap_index);
44 void llc_inv_all(int ap_index)
46 mmio_write_32(LLC_INV_WAY(ap_index), LLC_ALL_WAYS_MASK);
47 llc_cache_sync(ap_index);
50 void llc_disable(int ap_index)
52 llc_flush_all(ap_index);
53 mmio_write_32(LLC_CTRL(ap_index), 0);
57 void llc_enable(int ap_index, int excl_mode)
62 llc_inv_all(ap_index);
69 mmio_write_32(LLC_CTRL(ap_index), val);
73 int llc_is_exclusive(int ap_index)
77 reg = mmio_read_32(LLC_CTRL(ap_index));
86 void llc_runtime_enable(int ap_index)
90 reg = mmio_read_32(LLC_CTRL(ap_index));
103 llc_enable(ap_index, 1);
108 reg = mmio_read_32(CCU_HTC_CR(ap_index));
110 mmio_write_32(CCU_HTC_CR(ap_index), reg);
114 int llc_sram_enable(int ap_index, int size)
122 llc_enable(ap_index, 1);
123 llc_inv_all(ap_index);
129 mmio_write_32(LLC_TCN_LOCK(ap_index, tc), LLC_ALL_WAYS_MASK);
132 mmio_write_32(LLC_BANKED_MNT_AHR(ap_index), 0);
137 mmio_write_32(LLC_BLK_ALOC(ap_index),
146 void llc_sram_disable(int ap_index)
152 mmio_write_32(LLC_TCN_LOCK(ap_index, tc), 0);
155 llc_inv_all(ap_index);
158 int llc_sram_test(int ap_index, int size, char *msg)