Lines Matching defs:reg_base

44 	uintptr_t reg_base = imx_usdhc_params.reg_base;
58 	mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
59 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
62 	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);
68 	uintptr_t reg_base = imx_usdhc_params.reg_base;
70 	assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);
73 	mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);
76 	while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {
82 	mmio_write_32(reg_base + MMCBOOT, 0);
83 	mmio_write_32(reg_base + MIXCTRL, 0);
84 	mmio_write_32(reg_base + CLKTUNECTRLSTS, 0);
86 	mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT);
87 	mmio_write_32(reg_base + DLLCTRL, 0);
88 	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);
95 	mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR);
98 	mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE);
101 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK,
105 	mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));
112 	uintptr_t reg_base = imx_usdhc_params.reg_base;
120 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
124 		state = mmio_read_32(reg_base + PSTATE);
127 	while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)
130 	mmio_write_32(reg_base + INTSIGEN, 0);
183 	mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
184 	mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl);
185 	mmio_write_32(reg_base + XFERTYPE, xfertype);
189 		state = mmio_read_32(reg_base + INTSTAT);
208 		cmdrsp3 = mmio_read_32(reg_base + CMDRSP3);
209 		cmdrsp2 = mmio_read_32(reg_base + CMDRSP2);
210 		cmdrsp1 = mmio_read_32(reg_base + CMDRSP1);
211 		cmdrsp0 = mmio_read_32(reg_base + CMDRSP0);
217 		cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0);
224 			state = mmio_read_32(reg_base + INTSTAT);
237 		mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);
238 		while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)
242 			mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);
243 			while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)
249 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
256 	uintptr_t reg_base = imx_usdhc_params.reg_base;
261 		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
264 		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
272 	uintptr_t reg_base = imx_usdhc_params.reg_base;
274 	mmio_write_32(reg_base + DSADDR, buf);
275 	mmio_write_32(reg_base + BLKATT,
295 	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&