Lines Matching defs:reg
29 uint32_t reg = 0U;
33 reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS));
34 } while (CNF_GET_CTRL_BUSY(reg) != 0U);
40 uint32_t reg = 0U;
44 reg = mmio_read_32(CNF_CMDREG(TRD_STATUS));
45 reg &= (1U << (uint32_t)thread_id);
46 } while (reg != 0U);
53 uint32_t reg = 0U;
56 reg = mmio_read_32(CNF_CTRLPARAM(FEATURE));
57 nthreads = CNF_GET_NTHREADS(reg);
72 reg = mmio_read_32(CNF_CMDREG(CMD_STAT));
73 } while ((reg & CNF_CMPLT) == 0U);
76 if ((reg & err_mask) == 1U) {
77 ERROR("%s, CMD_STATUS:0x%x\n", __func__, reg);
96 uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT);
98 reg |= (thread_id << CNF_CMDREG0_TRD);
99 reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL);
100 reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR);
101 reg |= (CNF_CT_SET_FEATURE << CNF_CMDREG0_CMD);
102 mmio_write_32(CNF_CMDREG(CMD_REG0), reg);
117 uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT);
119 reg |= (thread_id << CNF_CMDREG0_TRD);
120 reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL);
121 reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR);
122 reg |= (CNF_CT_RESET_ASYNC << CNF_CMDREG0_CMD);
123 mmio_write_32(CNF_CMDREG(CMD_REG0), reg);
135 uint32_t reg = mmio_read_32(CNF_MINICTRL(DLL_PHY_CTRL));
137 reg &= ~(1 << CNF_DLL_PHY_RST_N);
138 mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg);
159 reg |= (1 << CNF_DLL_PHY_EXT_RD_MODE);
160 reg |= (1 << CNF_DLL_PHY_EXT_WR_MODE);
174 reg |= (1 << CNF_DLL_PHY_RST_N);
175 mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg);
208 uint32_t reg = 0U;
211 reg = mmio_read_32(CNF_CTRLPARAM(DEV_PARAMS0));
212 dev_info.type = CNF_GET_DEV_TYPE(reg);
217 dev_info.nluns = CNF_GET_NLUNS(reg);
220 reg = mmio_read_32(CNF_CTRLCFG(DEV_LAYOUT));
221 dev_info.npages_per_block = CNF_GET_NPAGES_PER_BLOCK(reg);
224 reg = mmio_read_32(CNF_CTRLCFG(TRANS_CFG1));
225 dev_info.sector_size = CNF_GET_SCTR_SIZE(reg);
226 dev_info.last_sector_size = CNF_GET_LAST_SCTR_SIZE(reg);
229 reg = mmio_read_32(CNF_CTRLPARAM(DEV_AREA));
230 dev_info.page_size = CNF_GET_PAGE_SIZE(reg);
231 dev_info.spare_size = CNF_GET_SPARE_SIZE(reg);
251 uint32_t reg = 0U;
256 reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS));
257 } while (CNF_GET_INIT_COMP(reg) == 0);
268 reg = mmio_read_32(CNF_DI(CONTROL));
269 reg |= (1 << CNF_DI_PAR_EN);
270 reg |= (1 << CNF_DI_CRC_EN);
271 mmio_write_32(CNF_DI(CONTROL), reg);
275 reg = mmio_read_32(CNF_CTRLCFG(DEV_STAT));
276 reg = reg & ~1;
277 mmio_write_32(CNF_CTRLCFG(DEV_STAT), reg);
304 uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT);
306 reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD);
307 reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL);
308 reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR);
309 reg |= (CNF_CT_ERASE << CNF_CMDREG0_CMD);
310 reg |= (((size-1) & 0xFF) << CNF_CMDREG0_CMD);
311 mmio_write_32(CNF_CMDREG(CMD_REG0), reg);
347 uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT);
349 reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD);
350 reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL);
351 reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR);
352 reg |= (CNF_DMA_MASTER_SEL << CNF_CMDREG0_DMA);
353 reg |= (CNF_CT_PAGE_READ << CNF_CMDREG0_CMD);
354 reg |= (((CNF_READ_SINGLE_PAGE-1) & 0xFF) << CNF_CMDREG0_CMD);
355 mmio_write_32(CNF_CMDREG(CMD_REG0), reg);