Lines Matching defs:value

165 	uint32_t value = 0;
169 	value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) |
175 			SDHC_CDNS_HRS05, value);
181 	value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) |
188 			SDHC_CDNS_HRS05, value);
194 	value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode))
198 			+ SDHC_CDNS_HRS05, value);
204 	value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay))
210 			+ SDHC_CDNS_HRS05, value);
218 	value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS05);
221 	value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT);
222 	mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS05, value);
226 		value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
227 		value |= SDHC_PHY_SW_RESET;
228 		mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
229 		value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
231 	} while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE);
235 	value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on))
242 			+ SDHC_CDNS_HRS05, value);
384 	uint32_t value = 0;
386 	value = mmio_read_32(addr);
387 	value &= ~SDHC_REG_MASK;
388 	value |= data;
389 	mmio_write_32(addr, value);
390 	value = mmio_read_32(addr);
391 	if (value != data) {
407 	uint32_t value = 0;
411 	value = (SDHC_RDDATA_EN(sdhc_reg->sdhc_rddata_en))
415 	ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
422 	value = (SDHC_HCSDCLKADJ(sdhc_reg->sdhc_hcsdclkadj));
423 	ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS10, value);
430 	value = (SDHC_WRDATA1_SDCLK_DLY(sdhc_reg->sdhc_wrdata1_sdclk_dly))
438 	ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS16, value);
445 	value = (SDHC_RW_COMPENSATE(sdhc_reg->sdhc_rw_compensate))
447 	ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS07, value);
519 	uint32_t value = 0;
521 	value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11);
522 	value &= ~(0xFFFF);
523 	value |= 0x0;
524 	mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, value);
540 	value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09);
541 	value &= ~SDHC_PHY_SW_RESET;
542 	mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value);
615 	uint32_t value;
796 		value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS12);
797 	} while (((value & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0));
805 		} while (((value & TRAN_COMP) == 0) && (timeout-- > 0));
808 	status_check = value & SRS12_ERR_MASK;