Lines Matching defs:priv
31 struct bcmspi_priv *priv = NULL;
34 priv = &spi_cfg;
35 priv->spi_mode = mode;
36 priv->state = QSPI_STATE_DISABLED;
37 priv->bspi_hw = QSPI_BSPI_MODE_REG_BASE;
38 priv->mspi_hw = QSPI_MSPI_MODE_REG_BASE;
44 priv->max_hz = max_hz;
47 mmio_write_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG, 0);
48 mmio_write_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG, 0);
49 mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0);
50 mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, 0);
51 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, 0);
54 spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
57 mmio_write_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG, spbr);
60 priv->mspi_16bit = 0;
61 mmio_write_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
64 (priv->spi_mode & MSPI_SPCR0_MSB_REG_MODE_MASK)); /* mode: CPOL / CPHA */
68 mmio_read_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG));
70 mmio_read_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG));
72 mmio_read_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG));
74 mmio_read_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG));
76 mmio_read_32(priv->mspi_hw + MSPI_SPCR2_REG));
77 VERBOSE("SPI: CLK: %d\n", priv->max_hz);
82 void bcmspi_enable_bspi(struct bcmspi_priv *priv)
84 if (priv->state != QSPI_STATE_BSPI) {
86 mmio_write_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0);
88 priv->state = QSPI_STATE_BSPI;
92 static int bcmspi_disable_bspi(struct bcmspi_priv *priv)
96 if (priv->state == QSPI_STATE_MSPI)
100 if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) &
105 priv->bspi_hw + BSPI_BUSY_STATUS_REG) &
107 mmio_write_32(priv->bspi_hw +
116 if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) &
124 priv->state = QSPI_STATE_MSPI;
131 struct bcmspi_priv *priv = &spi_cfg;
134 if (bcmspi_disable_bspi(priv) != 0)
142 struct bcmspi_priv *priv = &spi_cfg;
145 bcmspi_enable_bspi(priv);
148 static int mspi_xfer(struct bcmspi_priv *priv, uint32_t bytes,
166 priv->mspi_16bit = 0;
168 priv->mspi_16bit = 1;
178 if (priv->mspi_16bit) {
187 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
193 mmio_write_32(priv->mspi_hw +
205 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
208 mmio_write_32(priv->mspi_hw +
219 mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0);
220 mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, queues - 1);
224 mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
228 mmio_write_32(priv->mspi_hw + MSPI_STATUS_REG, 0);
230 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, MSPI_SPE);
232 mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG,
238 if (mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) &
244 if ((mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) &
252 if (priv->mspi_16bit) {
254 rx[i] = mmio_read_32(priv->mspi_hw +
261 rx[i] = mmio_read_32(priv->mspi_hw +
277 struct bcmspi_priv *priv;
283 priv = &spi_cfg;
285 if (priv->state == QSPI_STATE_DISABLED) {
300 if (bcmspi_disable_bspi(priv) != 0) {
305 mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 1);
310 ret = mspi_xfer(priv, bytes, tx, rx, flags);
314 mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0);