Lines Matching defs:base
59 uint32_t base;
64 .base = OTPC_MODE_REG,
69 uint32_t base;
77 static inline void set_command(uint32_t base, uint32_t command)
79 mmio_write_32(base + OTPC_COMMAND_OFFSET, command & OTPC_CMD_MASK);
82 static inline void set_cpu_address(uint32_t base, uint32_t addr)
84 mmio_write_32(base + OTPC_CPUADDR_REG_OFFSET, addr & OTPC_ADDR_MASK);
87 static inline void set_start_bit(uint32_t base)
89 mmio_write_32(base + OTPC_CMD_START_OFFSET, 1 << OTPC_CMD_START_START);
92 static inline void reset_start_bit(uint32_t base)
94 mmio_write_32(base + OTPC_CMD_START_OFFSET, 0);
97 static inline void write_cpu_data(uint32_t base, uint32_t value)
99 mmio_write_32(base + OTPC_CPU_WRITE_REG_OFFSET, value);
102 static int poll_cpu_status(uint32_t base, uint32_t value)
108 status = mmio_read_32(base + OTPC_CPU_STATUS_OFFSET);
124 set_command(priv->base, OTPC_CMD_ECC);
125 set_cpu_address(priv->base, OTPC_ECC_ADDR);
128 write_cpu_data(priv->base, OTPC_ECC_VAL);
130 write_cpu_data(priv->base, ~OTPC_ECC_VAL);
132 set_start_bit(priv->base);
133 ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
138 reset_start_bit(priv->base);
165 set_command(priv->base, OTPC_CMD_READ);
166 set_cpu_address(priv->base, address++);
167 set_start_bit(priv->base);
168 ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
175 *buf++ = mmio_read_32(priv->base +
180 reset_start_bit(priv->base);
191 priv->base = ocotp_cfg.base;
197 mmio_setbits_32(priv->base + OTPC_MODE_REG_OFFSET,
199 reset_start_bit(priv->base);